公开(公告)号：US20170271448A1

公开(公告)日：2017-09-21

申请号：US15598290

申请日：2017-05-17

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Sherry R. TAFT ,  Van H. LE ,  Sansaptak DASGUPTA ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  Matthew V. METZ ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/1037 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/02639 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/66795 ,  H01L29/785

Abstract: Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.

公开(公告)号：US20170012126A1

公开(公告)日：2017-01-12

申请号：US15119674

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Van H. LE ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Sansaptak DASGUPTA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

Abstract: Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

Abstract translation: 描述了具有选择性再生长顶端触点的垂直半导体器件和制造具有选择性再生长顶端触点的垂直半导体器件的方法。 例如，半导体器件包括具有表面的衬底。 第一源极/漏极区域设置在衬底的表面上。 垂直沟道区域设置在第一源极/漏极区域上并且具有与衬底的表面平行的第一宽度。 第二源极/漏极区域设置在垂直沟道区域上并且具有与第一宽度平行并且基本上大于第一宽度的第二宽度。 栅堆叠设置在垂直沟道区的一部分上并完全环绕。

公开(公告)号：US20160064491A1

公开(公告)日：2016-03-03

申请号：US14937819

申请日：2015-11-10

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz GARDNER ,  Seung Hoon SUNG ,  Robert S. Chau

IPC: H01L29/20 ,  H01L21/283 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/2003 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/201 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/802

Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

公开(公告)号：US20200266278A1

公开(公告)日：2020-08-20

申请号：US16279150

申请日：2019-02-19

Applicant: INTEL CORPORATION

Inventor： Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Han Wui THEN ,  Paul B. FISCHER ,  Walid M. HAFEZ

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/778 ,  H01L21/765 ,  H01L21/28 ,  H01L29/66 ,  H01L23/66

Abstract: A semiconductor device structure having a “T-shaped” gate structure is described. A narrower first portion supports high frequency processes (e.g., gigahertz wireless communications). A second portion of the gate structure has a second width greater than the first width. Lateral extensions (sometimes referred to as “field plates), thinner and wider than the second portion, extend from the second portion. This combination of a gate structure having a narrow first portion and a wider second portion improves the performance of the semiconductor device in applications that involve both high frequency and high power consumption.

公开(公告)号：US20200227545A1

公开(公告)日：2020-07-16

申请号：US16651327

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Stephan LEUSCHNER ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L21/765 ,  H01L21/285 ,  H01L29/66 ,  H03F3/45 ,  H03F3/21

Abstract: Gallium nitride (GaN) transistors with source and drain field plates are described. In an example, a transistor includes a gallium nitride (GaN) layer above a substrate, a gate structure over the GaN layer, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, the second side opposite the first side, a source field plate above the source region, and a drain field plate above the drain region.

公开(公告)号：US20200227544A1

公开(公告)日：2020-07-16

申请号：US16651326

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Stephan LEUSCHNER ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L21/765 ,  H01L21/285 ,  H01L29/66 ,  H03F3/21 ,  H03F3/45

Abstract: Gallium nitride (GaN) transistors with drain field plates and their methods of fabrication are described. In an example, a transistor includes a gallium nitride (GaN) layer above a substrate, a gate structure over the GaN layer, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, the second side opposite the first side, and a drain field plate above the drain region, wherein the drain field plate is not electrically coupled to the gate structure or the source region.

公开(公告)号：US20200066889A1

公开(公告)日：2020-02-27

申请号：US16321411

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/20 ,  H01L29/40

Abstract: Embodiments of the invention include a semiconductor device and methods of forming such devices. In an embodiment, the semiconductor device includes a source region, a drain region, and a channel region formed between the source region and drain region. In an embodiment, a first interlayer dielectric (ILD) may be formed over the channel region, and a first opening is formed through the first ILD. In an embodiment, a second ILD may be formed over the first ILD, and a second opening is formed through the second ILD. Embodiments of the invention include the second opening being offset from the first opening. Embodiments may also include a gate electrode formed through the first opening and the second opening. In an embodiment, the offset between the first opening and the second opening results in the formation of a field plate and a spacer that reduces a gate length of the semiconductor device.

公开(公告)号：US20190355843A1

公开(公告)日：2019-11-21

申请号：US16475220

申请日：2017-02-02

Applicant: INTEL CORPORATION

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L29/778 ,  H04B1/16 ,  H01L29/20 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762

Abstract: An apparatus, an integrated circuit die, and a method of fabricating a group III-nitride (III-N) integrated RF front-end circuit are disclosed. The apparatus includes a III-N integrated radio frequency (RF) front-end circuit that includes a semiconductor substrate, a plurality of functional blocks, each of the plurality of functional blocks comprising a III-N structure on the semiconductor substrate. The III-N integrated RF front-end circuit is to be coupled to an antenna.

公开(公告)号：US20190189611A1

公开(公告)日：2019-06-20

申请号：US16322082

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L27/02 ,  H01L29/20 ,  H01L29/778 ,  H01L29/861 ,  H01L29/417 ,  H01L29/205 ,  H01L29/167 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8258 ,  H01L29/08 ,  C23C16/30 ,  C23C16/04

CPC classification number: H01L27/0255 ,  C23C16/042 ,  C23C16/303 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/0332 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/8258 ,  H01L27/0248 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/36 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/66136 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/861 ,  H01L29/8611

Abstract: A semiconductor structure including a group III-N semiconductor material is disposed on a silicon substrate. A group III-N transistor structure is disposed on the group III-N semiconductor material. A well is disposed in the silicon substrate. The well has a first conductivity type. A doped region is disposed in the well. The doped region has a second conductivity type that is opposite to the first conductivity type. A first electrode is connected to the well of the second conductivity type and a second electrode is connected to the doped region having a first conductivity type. The well and the doped region form a PN diode. The well or the doped region is connected to the raised drain structure of the group III-N transistor.

公开(公告)号：US20180350921A1

公开(公告)日：2018-12-06

申请号：US15771985

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY

IPC: H01L29/267 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L29/778 ,  H01L21/02

CPC classification number: H01L21/8258 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/02568 ,  H01L21/02609 ,  H01L27/0924 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/78681

Abstract: Described herein are methods and structures integrating one or more TMDC crystal heteroepitaxially grown on one or more group III-Nitride (III-N) crystal. The TMDC crystal may be grown on a III-N heteroepitaxial crystal that has been grown on crystalline silicon substrate. One or more of III-N devices and silicon devices employing separated regions of the heteroepitaxial substrate may be integrated with a TMDC device fabricated on with the TMDC crystal. In some embodiments, impurity-doped III-N source/drain regions provide a low resistance coupling between metallization and a TMDC-channeled transistor.