公开(公告)号：US20210407902A1

公开(公告)日：2021-12-30

申请号：US16913859

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Gilbert DEWEY ,  Nazila HARATIPOUR ,  Mengcheng LU ,  Jitendra Kumar JHA ,  Jack T. KAVALIEROS ,  Matthew V. METZ ,  Scott B. CLENDENNING ,  Eric Charles MATTSON

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/78

Abstract: Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.

公开(公告)号：US20200287022A1

公开(公告)日：2020-09-10

申请号：US16881549

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Van H. LE ,  Scott B. CLENDENNING ,  Martin M. MITAN ,  Szuya S. LIAO

IPC: H01L29/66 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02

Abstract: Methods of selectively nitriding surfaces of semiconductor devices are disclosed. For example, a hardmask is formed on the top portion of the fins to create SOI structure. The hardmask may be formed by nitriding the top portion of the fin. In other embodiments, silicon nitride is grown on the top portion of the fin to form the hard masks. In another example, internal spacers are formed between adjacent nanowires in a gate-all-around structure. The internal spacers may be formed by nitriding the remaining interlayer material between the channel region and source and drain regions.

公开(公告)号：US20190189803A1

公开(公告)日：2019-06-20

申请号：US16271226

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Grant KLOSTER ,  Scott B. CLENDENNING ,  Rami HOURANI ,  Szuya S. LIAO ,  Patricio E. ROMERO ,  Florian GSTREIN

IPC: H01L29/78 ,  H01L21/32 ,  H01L21/3105 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L29/7851 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31133 ,  H01L21/32 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42368 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/786 ,  H01L29/78696

Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.

公开(公告)号：US20170058401A1

公开(公告)日：2017-03-02

申请号：US15119699

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： James M. BLACKWELL ,  Patricio E. ROMERO ,  Scott B. CLENDENNING ,  Grant M. KLOSTER ,  Florian GSTREIN ,  Harsono S. SIMKA ,  Paul A. ZIMMERMAN ,  Robert L. BRISTOL

IPC: C23C16/455 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  C23C16/18 ,  C23C16/48

CPC classification number: C23C16/45553 ,  C23C16/18 ,  C23C16/482 ,  H01L21/0337 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/66795

Abstract: Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.

Abstract translation: 描述了光辅助金属原子层沉积（ALD）和化学气相沉积（CVD）的前体和工艺设计。 在一个实例中，制造薄金属膜的方法包括将前体分子引入靠近基底上或表面的表面，每个前体分子具有被配体包围的一个或多个金属中心。 该方法还涉及通过使用光辅助方法从前体分子解离配体而在表面上沉积金属层。