公开(公告)号：US09368721B1

公开(公告)日：2016-06-14

申请号：US14553443

申请日：2014-11-25

Applicant: Intermolecular, Inc.

Inventor： Ashish Bodke ,  Mark Clark ,  Kevin Kashefi ,  Prashant B. Phatak

IPC: H01L45/00

CPC classification number: H01L45/1286 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/149

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). A structure including diamond-like carbon (DLC) can be used to surround the semiconductor layer of the MSM stack. The high thermal conductivity of the DLC structure may serve to remove heat from the selector device while higher currents are flowing through the selector element. This may lead to improved reliability and improved endurance.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少未选择器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以基于多层膜堆叠（例如金属 - 半导体 - 金属（MSM）堆叠）。 可以使用包括类金刚石碳（DLC）的结构来围绕MSM堆叠的半导体层。 DLC结构的高热导率可用于在较高的电流流过选择器元件时从选择器装置移除热量。 这可能导致改进的可靠性和耐久性。

公开(公告)号：US09343523B2

公开(公告)日：2016-05-17

申请号：US14599878

申请日：2015-01-19

Applicant: Intermolecular, Inc.

Inventor： Prashant B. Phatak

IPC: G11C11/36 ,  H01L49/02 ,  H01L45/00 ,  H01L27/24 ,  H01L21/02 ,  H01L21/283 ,  H01L21/3205

CPC classification number: H01L28/60 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/32055 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/00 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: MIMCAP diodes are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP diodes can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a barrier height modification layer, a low leakage dielectric layer and a high leakage dielectric layer. The layers can be sandwiched between two electrodes.

公开(公告)号：US20160133691A1

公开(公告)日：2016-05-12

申请号：US14534816

申请日：2014-11-06

Applicant: Intermolecular, Inc.

Inventor： Prashant B. Phatak ,  Hanhong Chen ,  Tony P. Chiang ,  Chien-Lan Hsueh ,  Monica Mathur

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/60

Abstract: Steps are taken to ensure that the bulk dielectric layer exhibits a crystalline phase before the deposition of a second electrode layer. The crystalline phase of the bulk dielectric layer facilitates the crystallization of the second electrode layer at lower temperature during a subsequent anneal treatment. In some embodiments, one or more interface layers are inserted between the bulk dielectric layer and the first electrode layer and/or the second electrode layer. The interface layers may act as an oxygen sink, facilitate the crystallization of the electrode layer at lower temperature during a subsequent anneal treatment, or provide barriers to leakage current through the film stack.

Abstract translation: 采取步骤以确保在沉积第二电极层之前体积电介质层呈现结晶相。 在随后的退火处理期间，体电介质层的结晶相有助于在较低温度下第二电极层的结晶。 在一些实施例中，一个或多个界面层插入在体电介质层和第一电极层和/或第二电极层之间。 界面层可以充当氧气沉淀器，在随后的退火处理期间促进电极层在较低温度下的结晶，或者提供通过膜堆叠的漏电流的障碍。

公开(公告)号：US09337238B1

公开(公告)日：2016-05-10

申请号：US14524801

申请日：2014-10-27

Applicant: Intermolecular, Inc.

Inventor： Kevin Kashefi ,  Ashish Bodke ,  Mark Clark ,  Prashant B. Phatak ,  Dipankar Pramanik

IPC: H01L27/24 ,  H01L33/50 ,  H01L33/32 ,  H01L33/30 ,  H01L33/28 ,  H01L33/40

CPC classification number: H01L27/2409 ,  H01L27/15 ,  H01L33/285 ,  H01L33/30 ,  H01L33/32 ,  H01L33/40 ,  H01L33/502 ,  H01L45/08

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a photo-luminescent or electro-luminescent material. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or combinations thereof.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以基于多层膜堆叠（例如金属 - 半导体 - 金属（MSM）堆叠）。 选择元件的半导体层可以包括光致发光或电致发光材料。 MSM的导电材料可以包括钨，氮化钛，碳或其组合。

公开(公告)号：US20160118440A1

公开(公告)日：2016-04-28

申请号：US14524801

申请日：2014-10-27

Applicant: Intermolecular, Inc.

Inventor： Kevin Kashefi ,  Ashish Bodke ,  Mark Clark ,  Prashant B. Phatak ,  Dipankar Pramanik

IPC: H01L27/24 ,  H01L33/40 ,  H01L33/32 ,  H01L33/50 ,  H01L33/28 ,  H01L33/30

CPC classification number: H01L27/2409 ,  H01L27/15 ,  H01L33/285 ,  H01L33/30 ,  H01L33/32 ,  H01L33/40 ,  H01L33/502 ,  H01L45/08

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a photo-luminescent or electro-luminescent material. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or combinations thereof.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以基于多层膜堆叠（例如金属 - 半导体 - 金属（MSM）堆叠）。 选择元件的半导体层可以包括光致发光或电致发光材料。 MSM的导电材料可以包括钨，氮化钛，碳或其组合。

公开(公告)号：US20150001676A1

公开(公告)日：2015-01-01

申请号：US14491080

申请日：2014-09-19

Applicant: Intermolecular, Inc.

Inventor： Venkat Ananthan ,  Imran Hashim ,  Prashant B. Phatak

IPC: H01L27/24 ,  H01L49/02

CPC classification number: H01L27/2418 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L28/40 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633

Abstract: MIMCAP devices are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP devices can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a low defect dielectric layer, a high defect dielectric layer, sandwiched between two electrodes having different work function values.

Abstract translation: 提供了可适用于存储器件应用的MIMCAP器件，例如用于交叉点存储器阵列的电流选择器装置。 与MIMCAP隧道二极管相比，MIMCAP器件与肖特基二极管相比可以具有更低的热量预算，并且可控制的较低势垒高度和较低的串联电阻。 MIMCAP二极管可以包括夹在具有不同功函数值的两个电极之间的低缺陷电介质层，高缺陷电介质层。

公开(公告)号：US20140302659A1

公开(公告)日：2014-10-09

申请号：US14312628

申请日：2014-06-23

Applicant: Intermolecular, Inc.

Inventor： Prashant B. Phatak ,  Ronald J. Kuse ,  Jinhong Tong

IPC: H01L45/00

CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1641

Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include preventing formation of interfacial layers, and creating electronic defects in a dielectric film. Suppressing interfacial layers in an electrode reduces forming voltage. Electronic defects in a dielectric film foster formation of conductive pathways.

Abstract translation: 制造具有降低的成形电压的RRAM电阻式开关元件的方法包括阻止形成界面层，并在电介质膜中产生电子缺陷。 抑制电极中的界面层降低成形电压。 电介质膜中的电子缺陷促进导电通路的形成。

公开(公告)号：US20140264252A1

公开(公告)日：2014-09-18

申请号：US14294519

申请日：2014-06-03

Applicant: Intermolecular, Inc.

Inventor： Imran Hashim ,  Venkat Ananthan ,  Tony P. Chiang ,  Prashant B. Phatak

IPC: H01L27/24 ,  H01L29/872

CPC classification number: H01L27/2418 ,  H01L27/2409 ,  H01L29/872 ,  H01L45/10

Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.

Abstract translation: 可适用于存储器件应用的选择器器件可在低电压下具有低漏电流，以减少非选定器件的漏电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 在一些实施例中，选择器装置可以包括第一电极，三层电介质层和第二电极。 三层电介质层可以包括夹在两个较低的漏电介质层之间的高泄漏电介质层。 低泄漏层可以起到限制低电压下选择器装置的电流的作用。 高泄漏电介质层可以用于在高电压下增强选择器装置上的电流。

公开(公告)号：US20140138602A1

公开(公告)日：2014-05-22

申请号：US14163970

申请日：2014-01-24

Applicant: Intermolecular, Inc.

Inventor： Michael Miller ,  Tony P. Chiang ,  Prashant B. Phatak

IPC: H01L45/00

CPC classification number: H01L45/122 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/55 ,  G11C2213/56 ,  H01L21/265 ,  H01L21/322 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165 ,  H01L45/1658 ,  H01L45/1675

Abstract: Controlled localized defect paths for resistive memories are described, including a method for forming controlled localized defect paths including forming a first electrode forming a metal oxide layer on the first electrode, masking the metal oxide to create exposed regions and concealed regions of a surface of the metal oxide, and altering the exposed regions of the metal oxide to create localized defect paths beneath the exposed regions.

Abstract translation: 描述了用于电阻存储器的受控局部缺陷路径，包括用于形成受控局部缺陷路径的方法，包括形成在第一电极上形成金属氧化物层的第一电极，掩蔽金属氧化物以产生暴露区域和隐藏区域 金属氧化物，并且改变金属氧化物的暴露区域以在暴露区域下方产生局部缺陷路径。

公开(公告)号：US20140084236A1

公开(公告)日：2014-03-27

申请号：US14091594

申请日：2013-11-27

Applicant: Intermolecular Inc.

Inventor： Nobumichi Fuchigami ,  Pragati KUMAR ,  Prashant B. Phatak

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616

Abstract: ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.