公开(公告)号：US11688636B2

公开(公告)日：2023-06-27

申请号：US17351307

申请日：2021-06-18

Applicant: International Business Machines Corporation

Inventor： Somnath Ghosh ,  Karen Elizabeth Petrillo ,  Cody J. Murray ,  Ekmini Anuja De Silva ,  Chi-Chun Liu ,  Dominik Metzler ,  John Christopher Arnold

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532

CPC classification number: H01L21/76892 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76837 ,  H01L23/53242

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of metal lines on substrate, forming a sacrificial dielectric material layer between the metal lines, forming a hardmask over at least one of the metal lines, etching at least one of the metal lines that is not covered by the hardmask, treating the sacrificial dielectric material layer to soften the layer. The method also includes removing the treated sacrificial dielectric material layer.

公开(公告)号：US11670580B2

公开(公告)日：2023-06-06

申请号：US17461096

申请日：2021-08-30

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Hsueh-Chung Chen ,  Junli Wang ,  Mary Claire Silvestre ,  Chi-Chun Liu

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L28/90

Abstract: Structures are provided that include a metal-insulator-metal capacitor (MIMCAP) present in the back-end-of-the-line (BEOL). The MIMCAP includes at least one of the bottom electrode and the top electrode having a via portion and a base portion that is formed utilizing a subtractive via etch process. Less via over etching occurs resulting in improved critical dimension control of the bottom and/or top electrodes that are formed by the subtractive via etch process. No bottom liner is present in the MIMCAP thus improving the resistance/capacitance of the device. Also, and in some embodiments, a reduced foot-print area is possible to bring the via portion of the bottom electrode closer to the top electrode.

公开(公告)号：US11501969B2

公开(公告)日：2022-11-15

申请号：US16253429

申请日：2019-01-22

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Yongan Xu ,  Ekmini Anuja De Silva ,  Ashim Dutta ,  Chi-Chun Liu

IPC: H01L21/033

Abstract: A method of making a semiconductor device includes depositing an oxide material on a patterned mask arranged on a substrate. The method further includes removing a portion of the oxide material such that the patterned mask is exposed. The method also includes removing the patterned mask such that the substrate is exposed between areas of remaining oxide material.

公开(公告)号：US11226561B2

公开(公告)日：2022-01-18

申请号：US16101411

申请日：2018-08-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chi-Chun Liu ,  Indira Seshadri ,  Kristin Schmidt ,  Nelson Felix ,  Daniel Sanders ,  Jing Guo ,  Ekmini Anuja De Silva ,  Hoa Truong

IPC: G03F7/11 ,  G03F7/09 ,  G03F7/004

Abstract: A self-priming resist may be formed from a first random copolymer forming a resist and a polymer brush having the general formula poly(A-r-B)-C-D, wherein A is a first polymer unit, B is a second polymer unit, wherein A and B are the same or different polymer units, C is a cleavable unit, D is a grafting group and r indicates that poly(A-r-B) is a second random copolymer formed from the first and second polymer units. The first random copolymer may be the same or different from the second random polymer. The self-priming resist can create a one-step method for forming an adhesion layer and resist by using the resist/brush blend.

公开(公告)号：US10892328B2

公开(公告)日：2021-01-12

申请号：US16291443

申请日：2019-03-04

Applicant: International Business Machines Corporation

Inventor： Yi Song ,  Zhenxing Bi ,  Kangguo Cheng ,  Chi-Chun Liu

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/764 ,  H01L27/088 ,  H01L29/10 ,  H01L29/06

Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack over a substrate, the nanosheet stack including alternating sacrificial and channel layers, the channel layers providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the nanosheet stack and a portion of the substrate, and forming indents in sidewalls of the sacrificial layers at sidewalls of the vertical fins. The method further includes forming nanosheet extension regions in portions of the channel layers which extend from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins, the nanosheet extension regions increasing in thickness from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins. The method further includes forming inner spacers using a conformal deposition process that forms air gaps in spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers.

公开(公告)号：US20200343186A1

公开(公告)日：2020-10-29

申请号：US16397250

申请日：2019-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Chih-Chao Yang ,  Chi-Chun Liu ,  Kangguo Cheng

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/522

Abstract: Integrated chips and methods for forming vias in the same include forming a multi-layer isolation structure on an underlying layer. The multi-layer isolation structure includes a first isolation layer around a second isolation layer. Conductive material is formed around the multi-layer isolation structure. The first isolation layer is etched back to expose at least a portion of a sidewall of the conductive material. A conductive via is formed to contact a top surface and the exposed portion of the sidewall of the conductive material.

公开(公告)号：US10707326B2

公开(公告)日：2020-07-07

申请号：US16282384

申请日：2019-02-22

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Sanjay Mehta ,  Luciana Meli ,  Muthumanickam Sankarapandian ,  Kristin Schmidt ,  Ankit Vora

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/08 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417

Abstract: A vertical field-effect transistor and a method for fabricating the same. The vertical field-effect transistor includes a substrate and a bottom source/drain region. The vertical field-effect transistor also includes at least one fin structure, and further includes a bottom spacer layer. The bottom spacer layer has a substantially uniform thickness with a thickness variation of less than 3 nm. A gate structure contacts the bottom spacer layer and at least one fin structure. The method includes forming a structure including a substrate, a source/drain region, and one or more fins. A polymer brush spacer is formed in contact with at least sidewalls of the one or more fins. A polymer brush layer is formed in contact with at least the source/drain region and the polymer brush spacer. The polymer brush spacer is removed. Then, the polymer brush layer is reflowed to the sidewalls of the at least one fin.

公开(公告)号：US20200119168A1

公开(公告)日：2020-04-16

申请号：US16157518

申请日：2018-10-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yi Song ,  Junli Wang ,  Chi-Chun Liu ,  Liying Jiang

IPC: H01L29/66 ,  H01L29/205 ,  H01L29/08 ,  H01L29/51 ,  H01L29/78 ,  H01L21/308 ,  H01L21/306

Abstract: Semiconductor devices and methods of forming the same include forming a doped drain structure having a first conductivity type on sidewalls of an intrinsic channel layer. An opening is etched in a middle of the channel layer. A doped source structure is formed having a second conductivity type in the opening of the channel layer.

公开(公告)号：US10580652B2

公开(公告)日：2020-03-03

申请号：US16058088

申请日：2018-08-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John C. Arnold ,  Anuja E. DeSilva ,  Nelson M. Felix ,  Chi-Chun Liu ,  Yann A. M. Mignot ,  Stuart A. Sieg

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/8234

Abstract: Methods of forming fins include masking a region on a three-color hardmask fin pattern, leaving a fin of a first color exposed. The exposed fin of the first color is etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into a fin base layer using the fins of the first color and the fins of the third color.

公开(公告)号：US20190333774A1

公开(公告)日：2019-10-31

申请号：US16508691

申请日：2019-07-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sean D. Burns ,  Nelson M. Felix ,  Chi-Chun Liu ,  Yann A.M. Mignot ,  Stuart A. Sieg

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/8234 ,  H01L21/033

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.