公开(公告)号：US20200381306A1

公开(公告)日：2020-12-03

申请号：US16429371

申请日：2019-06-03

Applicant: International Business Machines Corporation

Inventor： Chanro Park ,  Kangguo Cheng ,  Ruilong Xie ,  Choonghyun Lee

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/768

Abstract: Embodiments of the present invention are directed to a gate cap last process for forming a self-aligned contact. This gate cap last process allows for a thin SAC cap, as the SAC cap only needs to prevent a short between the metallization contact and the gate. In a non-limiting embodiment of the invention, a gate is formed over a channel region of a fin. The gate can include a gate spacer. A sacrificial contact is formed on a top surface of a source or drain (S/D) region of a substrate. The sacrificial contact is positioned directly adjacent to a sidewall of the gate spacer. An exposed surface of the gate is recessed to form a recessed gate surface and a self-aligned contact (SAC) cap is formed on the recessed gate surface. The sacrificial contact is replaced with a S/D contact.

公开(公告)号：US20200373434A1

公开(公告)日：2020-11-26

申请号：US16421418

申请日：2019-05-23

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Alexander Reznicek ,  Xin Miao ,  Jingyun Zhang

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66 ,  H01L21/22

Abstract: A vertical field effect transistor (VFET) has a top source/drain (S/D) with a first region having a first area and a first capacitance and a second region having a second area and a second capacitance. A first top spacer on a gate cross section area. A second top spacer with a varying thickness is disposed the first top spacer. Both the first and second top spacers are between the top S/D and the gate cross section area. Due to the varying thickness of the second spacer with the smaller thickness closer to the fin, the separation distance between the larger, first area and the gate cross section area is greater than the separation distance between the smaller, second area and the gate cross section area. Therefore, the first capacitance is reduced because of the larger separation distance and the second capacitance is reduced because of the smaller second area. The smaller thickness of the second top spacer being closer to the fin allows dopants to diffuse a shorter distance when forming a junction between the top S/D and the channel of the VFET.

公开(公告)号：US20200312704A1

公开(公告)日：2020-10-01

申请号：US16365927

申请日：2019-03-27

Applicant: International Business Machines Corporation

Inventor： Soon-Cheon Seo ,  Injo Ok ,  Alexander Reznicek ,  Choonghyun Lee

IPC: H01L21/764 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L27/24 ,  H01L45/00

Abstract: A method of forming a memory structure includes forming an opening on opposing sides of a plurality of memory pillars disposed on a substrate, the opening extends through a capping layer located above a first dielectric layer and a top portion of an oxide layer, the oxide layer is located between the first dielectric layer and an encapsulation layer on the substrate, the encapsulation layer surrounds the plurality of pillars, removing the oxide layer from areas of the memory structure located between the memory pillars, above the encapsulation layer and below the first dielectric layer, after removing the oxide layer a gap remains within the areas of the memory structure, and forming a second dielectric directly above the capping layer, wherein the second dielectric layer pinches off the opening to form airgaps.

公开(公告)号：US20200295147A1

公开(公告)日：2020-09-17

申请号：US16351729

申请日：2019-03-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： RUQIANG BAO ,  HEMANTH JAGANNATHAN ,  Paul Charles Jamison ,  Choonghyun Lee ,  Sanjay C. Mehta ,  Vijay Narayanan

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/778

Abstract: A technique relates to a semiconductor device. A gate stack is formed on a fin, the gate stack being formed to have a length in a vertical direction. A gate contact is formed adjacent to the gate stack for the length of the gate stack in the vertical direction.

公开(公告)号：US10763431B2

公开(公告)日：2020-09-01

申请号：US16193851

申请日：2018-11-16

Applicant: International Business Machines Corporation

Inventor： Injo Ok ,  Choonghyun Lee ,  Chih-Chao Yang ,  Seyoung Kim ,  Soon-Cheon Seo

IPC: H01L49/02 ,  H01L45/00 ,  H01L43/02 ,  H01L27/24 ,  H01L43/12 ,  H01L27/11502 ,  H01L27/22

Abstract: Semiconductor structures are provided that include a memory device buried within interconnect dielectric materials and in which a combination of a compressive metal-containing layer and a tensile metal-containing layer have been used to minimize wafer bow and litho overlay shift as well as a method of forming such semiconductor structures.

公开(公告)号：US10756176B2

公开(公告)日：2020-08-25

申请号：US16188993

申请日：2018-11-13

Applicant: International Business Machines Corporation

Inventor： Pouya Hashemi ,  Takashi Ando ,  Jingyun Zhang ,  Choonghyun Lee ,  Alexander Reznicek

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L21/02 ,  H01L29/786 ,  H01L21/28 ,  H01L29/423

Abstract: A stacked nanosheet semiconductor device and method of forming are provided. In an illustrative embodiment, a gate all around (GAA) stacked nanosheet field effect transistor (FET) includes a plurality of stacked semiconductor channel nanosheet layers and a dummy nanosheet layer formed above a top one of the stacked semiconductor channel nanosheet layers, the dummy nanosheet formed from a dielectric material. The GAA stacked nanosheet FET also includes a high dielectric constant (high-k) material formed around each of the plurality of stacked semiconductor channel nanosheet layers and around the dummy nanosheet layer and a first work function (WF) metal formed around the plurality of stacked semiconductor channel nanosheet layers and the dummy nanosheet layer.

公开(公告)号：US10748962B2

公开(公告)日：2020-08-18

申请号：US15960670

申请日：2018-04-24

Applicant: International Business Machines Corporation

Inventor： Soon-Cheon Seo ,  Seyoung Kim ,  Injo Ok ,  Choonghyun Lee ,  Kisup Chung

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

Abstract: A method of forming a bottom electrode for MRAM comprises: depositing a conductive material into a trench in a substrate and planarizing; depositing a selective cap on the conductive material; depositing a layer of high stress material on upper surfaces of the substrate and the cap; patterning the high stress material to remove the layer of high stress material on the upper surfaces of the substrate and leaving the layer of high stress material on the upper surfaces of the cap; depositing a layer of dielectric material on the upper surfaces of the substrate and on upper surfaces of the high stress material on the cap; planarizing the layer of dielectric material; and forming a magnetic tunnel junction stack on the dielectric material over the conductive material.

公开(公告)号：US20200258786A1

公开(公告)日：2020-08-13

申请号：US16270174

申请日：2019-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Jingyun Zhang ,  Alexander Reznicek ,  Choonghyun Lee ,  Pouya Hashemi

IPC: H01L21/8234 ,  H01L21/324 ,  H01L21/02 ,  H01L21/285 ,  H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L21/3065

Abstract: A method is presented for attaining different gate dielectric thicknesses across a plurality of field effect transistor (FET) devices. The method includes forming interfacial and high-k dielectric layers around alternate semiconductor layers of the plurality of FET devices, pinching off gaps between the alternate semiconductor layers by depositing a high work function capping layer over the plurality of FET devices, selectively removing the high work function capping layer from a first set of the plurality of FET devices, depositing a sacrificial capping layer, with the sacrificial capping layer leaving gaps between the alternate semiconductor layers of the first set of the plurality of FET devices, depositing an oxygen blocking layer, and annealing the plurality of FET devices to create different gate dielectric thicknesses for each of the plurality of FET devices.

公开(公告)号：US10734479B1

公开(公告)日：2020-08-04

申请号：US16255430

申请日：2019-01-23

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Choonghyun Lee ,  Takashi Ando ,  Jingyun Zhang ,  Pouya Hashemi

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L29/167 ,  H01L29/165 ,  H01L29/78

Abstract: A FinFET having an asymmetric threshold voltage distribution is provided by modifying a portion of the channel region of a semiconductor fin that is nearest to the drain side with an epitaxial semiconductor material layer. In some embodiments, the channel region of the semiconductor fin nearest to the drain side is trimmed prior to forming the epitaxial semiconductor material layer.

公开(公告)号：US10734447B2

公开(公告)日：2020-08-04

申请号：US16167099

申请日：2018-10-22

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Alexander Reznicek ,  Choonghyun Lee ,  Jingyun Zhang

IPC: H01L27/24 ,  H01L45/00 ,  G06N3/063

Abstract: Techniques regarding FET 1T2R unit cells are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a first resistive random-access memory unit operably coupled to a field-effect transistor by a first extrinsic semiconductor layer. The system can also comprise a second resistive random-access memory unit operably coupled to the field-effect transistor by a second extrinsic semiconductor layer.