公开(公告)号：US20180114750A1

公开(公告)日：2018-04-26

申请号：US15816414

申请日：2017-11-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Elbert Huang ,  Joe Lee ,  Christopher J. Penny

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53238

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving copper (Cu), selectively recessing the Cu at one or more of the trenches corresponding to circuit locations requiring electromigration (EM) short-length, and forming self-aligned conducting caps over the one or more trenches where the Cu has been selectively recessed. The conducting caps can be tantalum nitride (TaN) caps. The method further includes forming a via extending into each of the trenches for receiving Cu. Additionally, the via for trenches including recessed Cu extends to the self-aligned conducting cap, whereas the via for trenches including non-recessed Cu extends to a top surface of the Cu.

公开(公告)号：US20180114723A1

公开(公告)日：2018-04-26

申请号：US15335122

申请日：2016-10-26

Applicant: International Business Machines Corporation

Inventor： Benjamin David Briggs ,  Joe Lee ,  Theodorus Eduardus Standaert

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238

Abstract: A method of forming fully aligned vias in a semiconductor device includes forming an Mx level interconnect line embedded in an Mx interlevel dielectric (ILD). The Mx level interconnect is recessed below the Mx interlevel dielectric or a dielectric is selectively deposited on the Mx interlevel dielectric. The method also includes laterally etching the exposed upper portion of the Mx interlevel dielectric bounding the recess or laterally etching the selectively deposited dielectric. A dielectric cap layer and an Mx+1 level interlevel dielectric is deposited on top of the Mx interlevel dielectric, and a via opening is formed.

公开(公告)号：US09390967B2

公开(公告)日：2016-07-12

申请号：US14567567

申请日：2014-12-11

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Joe Lee ,  Yann Mignot ,  Brown C. Peethala

IPC: H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76843

Abstract: A selective wet etching process is used, prior to air gap opening formation, to remove a sacrificial nitride layer from over a first region of an interconnect dielectric material containing a plurality of first conductive metal structures utilizing a titanium nitride hard mask portion located over a second region of the interconnect dielectric material as an etch mask. The titanium nitride hard mask portion located over the second region of the interconnect dielectric material is thereafter removed, again prior to air gap opening formation, utilizing another wet etch process. The wet etching processes are used instead of reactive ion etching.

Abstract translation: 在气隙开口形成之前使用选择性湿法蚀刻工艺，以从包含多个第一导电金属结构的互连电介质材料的第一区域上方移除牺牲氮化物层，所述第一导电金属结构利用位于第二层上的氮化钛硬掩模部分 互连电介质材料的区域作为蚀刻掩模。 此后，在气隙开口形成之前，再次移除位于互连电介质材料的第二区域之上的氮化钛硬掩模部分，利用另一湿蚀刻工艺。 使用湿蚀刻工艺代替反应离子蚀刻。

公开(公告)号：US09349687B1

公开(公告)日：2016-05-24

申请号：US14975725

申请日：2015-12-19

Applicant: International Business Machines Corporation

Inventor： Stephen M. Gates ,  Elbert E. Huang ,  Joe Lee ,  Son V. Nguyen ,  Brown C. Peethala ,  Christopher J. Penny ,  Deepika Priyadarshini

IPC: H01L21/768 ,  H01L23/528 ,  H01L29/06 ,  H01L23/532 ,  H01L21/308

CPC classification number: H01L21/3081 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76849 ,  H01L23/4821 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: After forming a manganese (Mn)-containing cap layer over interconnects embedded in an interlevel dielectric (ILD) layer, a lithographic stack is formed over the Mn-containing cap layer. The lithographic stack is subsequently patterned to expose a portion of the Mn-containing cap layer that overlies a subset of the interconnects between which the air gaps are to be formed. A portion of the ILD layer located between the subset of the interconnects is damaged through the exposed portion of the Mn-containing cap layer. The damaged portion of the ILD layer is subsequently removed to form openings between the subset of the interconnects. The Mn-containing cap layer acts as a temporary protection layer preventing erosion of the underlying interconnects during the air gap formation.

Abstract translation: 在嵌入层间电介质（ILD）层的互连上形成含有锰（Mn）的覆盖层之后，在含Mn覆盖层上形成光刻堆叠。 随后将光刻堆叠图案化以暴露覆盖在其间将要形成气隙的互连子集之间的含Mn覆盖层的一部分。 位于互连子集之间的ILD层的一部分通过含Mn覆盖层的暴露部分而损坏。 随后去除ILD层的损坏部分，以在互连子集之间形成开口。 含Mn的盖层用作临时保护层，防止在气隙形成期间底层互连的侵蚀。

公开(公告)号：US20220028797A1

公开(公告)日：2022-01-27

申请号：US17493486

申请日：2021-10-04

Applicant: International Business Machines Corporation

Inventor： Kenneth Chun Kuen Cheng ,  Koichi Motoyama ,  Kisik Choi ,  Cornelius Brown Peethala ,  Hosadurga Shobha ,  Joe Lee

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/02 ,  H01L21/768

Abstract: Bottom barrier free interconnects are provided. In one aspect, an interconnect structure includes: metal lines embedded in a dielectric; an interlayer dielectric (ILD) disposed over the metal lines; interconnects formed in the ILD on top of the metal lines; a barrier layer separating the interconnects from the ILD, wherein the barrier layer is absent in between the interconnects and the metal lines; and a selective capping layer disposed on the interconnects.

公开(公告)号：US11164815B2

公开(公告)日：2021-11-02

申请号：US16586947

申请日：2019-09-28

Applicant: International Business Machines Corporation

Inventor： Kenneth Chun Kuen Cheng ,  Koichi Motoyama ,  Kisik Choi ,  Cornelius Brown Peethala ,  Hosadurga Shobha ,  Joe Lee

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/02 ,  H01L21/768

Abstract: Techniques to enable bottom barrier free interconnects without voids. In one aspect, a method of forming interconnects includes: forming metal lines embedded in a dielectric; depositing a sacrificial dielectric over the metal lines; patterning vias and trenches in the sacrificial dielectric down to the metal lines, with the trenches positioned over the vias; lining the vias and trenches with a barrier layer; depositing a conductor into the vias and trenches over the barrier layer to form the interconnects; forming a selective capping layer on the interconnects; removing the sacrificial dielectric in its entirety; and depositing an interlayer dielectric (ILD) to replace the sacrificial dielectric. An interconnect structure is also provided.

公开(公告)号：US10831489B2

公开(公告)日：2020-11-10

申请号：US16110061

申请日：2018-08-23

Applicant: International Business Machines Corporation

Inventor： Kenneth L. Ward ,  Susan E. Eisen ,  Dung Q. Nguyen ,  Glenn O. Kincaid ,  Joe Lee ,  Deepak K. Singh

IPC: G06F9/50 ,  G06F9/34 ,  G06F9/30 ,  G06F9/38

Abstract: Method and apparatus for completing atomic instructions in a microprocessor may be provided by identifying from a program-ordered Instruction Completion Table (ICT) a last entry in a completion window of instructions for completion in a current clock cycle of a processor; in response to determining that the last entry includes an atomic instruction that straddles the completion window: excluding the last entry from completion during the current clock cycle; completing instructions in the completion window for the current clock cycle; and shifting the completion window to include the last entry and a next entry adjacent to the last entry in the ICT in a next clock cycle.

公开(公告)号：US10725786B2

公开(公告)日：2020-07-28

申请号：US16109952

申请日：2018-08-23

Applicant: International Business Machines Corporation

Inventor： Kenneth L. Ward ,  Susan E. Eisen ,  Dung Q. Nguyen ,  Glenn O. Kincaid ,  Joe Lee ,  Deepak K. Singh

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/34

Abstract: Method and apparatus for a completion mechanism for a microprocessor are provided by marking entries in a section of an Instruction Completion Table (ICT) as ready to complete using corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion in a current clock cycle; performing a counting leading ones on an RTC vector that organizes the RTC status bits according to a program order for completing the entries to determine a count leading ones pointer that indicates an end of the entries in the ICT that are ready for completion in the current clock cycle; completing instructions included in the entries between the tail pointer and the count leading ones pointer in one clock cycle; and updating the tail pointer to a value of the count leading ones pointer for a subsequent clock cycle.

公开(公告)号：US10672705B2

公开(公告)日：2020-06-02

申请号：US16671445

申请日：2019-11-01

Applicant: International Business Machines Corporation

Inventor： Yongan Xu ,  Junli Wang ,  Yann Mignot ,  Joe Lee

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  H01L21/768 ,  H01L21/3105

Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect level having a conductive metal layer formed in a first dielectric layer. In the method, a cap layer is formed on the first interconnect level, and a second interconnect level including a second dielectric layer is formed on the cap layer. The method also includes forming a third interconnect level including a third dielectric layer on the second interconnect level. An opening is formed through the second and third interconnect levels and over the conductive metal layer. Sides of the opening are lined with a spacer material, and a portion of the cap layer at a bottom of the opening is removed from a top surface of the conductive metal layer. The spacer material is removed from the opening, and a conductive material layer is deposited in the opening on the conductive metal layer.

公开(公告)号：US20200066632A1

公开(公告)日：2020-02-27

申请号：US16671445

申请日：2019-11-01

Applicant: International Business Machines Corporation

Inventor： Yongan Xu ,  Junli Wang ,  Yann Mignot ,  Joe Lee

IPC: H01L23/522 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  H01L21/768 ,  H01L21/3105

Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect level having a conductive metal layer formed in a first dielectric layer. In the method, a cap layer is formed on the first interconnect level, and a second interconnect level including a second dielectric layer is formed on the cap layer. The method also includes forming a third interconnect level including a third dielectric layer on the second interconnect level. An opening is formed through the second and third interconnect levels and over the conductive metal layer. Sides of the opening are lined with a spacer material, and a portion of the cap layer at a bottom of the opening is removed from a top surface of the conductive metal layer. The spacer material is removed from the opening, and a conductive material layer is deposited in the opening on the conductive metal layer.