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    SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR
    32.
    发明申请
    SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR 有权
    选择性的本地金属层形成用于改进的电化学行为

    公开(公告)号：US20140203436A1

    公开(公告)日：2014-07-24

    申请号：US13964772

    申请日：2013-08-12

    Applicant: International Business Machines Corporation

    Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Lijuan Zhang

    IPC: H01L23/532 ,  H01L21/768

    CPC classification number: H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.

    Abstract translation: 一种形成集成电路器件的布线结构的方法包括在层间电介质（ILD）层内形成第一金属线，并在与第一金属线相邻的ILD层中形成第二金属线; 掩蔽所述第一和第二金属线的选定区域; 以周期性间隔选择性地在第一和第二金属线的暴露区域上电镀金属帽区域，使得单个金属线的相邻金属帽区域之间的间隔对应于临界长度L，在该临界长度L处，背应力梯度平衡电迁移力 在各个金属线上，以抑制电子的质量传递; 并且其中所述第一金属线的金属帽区域沿着共同的纵向轴线相对于所述第二金属线的金属帽区域以交错位置形成。

    STRUCTURE AND METHOD FOR IN-LINE DEFECT NON-CONTACT TESTS
    33.
    发明申请
    STRUCTURE AND METHOD FOR IN-LINE DEFECT NON-CONTACT TESTS 有权
    用于在线缺陷非接触测试的结构和方法

    公开(公告)号：US20140152337A1

    公开(公告)日：2014-06-05

    申请号：US13705213

    申请日：2012-12-05

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC: G01R31/26

    CPC classification number: H01L22/14 ,  G01R31/024 ,  G01R31/2644 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A system, method and apparatus may comprise a wafer having a plurality of spiral test structures located on the kerf of the wafer. The spiral test structure may comprise a spiral connected at either end by a capacitor to allow the spiral test structure to resonate. The spiral structures may be located on a first metal layer or on multiple metal layers. The system may further incorporate a test apparatus having a frequency transmitter and a receiver. The test apparatus may be a sensing spiral which may be placed over the spiral test structures. A controller may provide a range of frequencies to the test apparatus and receiving the resonant frequencies from the test apparatus. The resonant frequencies will be seen as reductions in signal response at the test apparatus.

    Abstract translation: 系统，方法和装置可以包括具有位于晶片的切口上的多个螺旋测试结构的晶片。 螺旋测试结构可以包括在任一端由电容器连接的螺旋，以允许螺旋测试结构共振。 螺旋结构可以位于第一金属层上或多个金属层上。 该系统还可以包括具有频率发射器和接收器的测试装置。 测试装置可以是可以放置在螺旋测试结构上方的感测螺旋。 控制器可以向测试设备提供一定范围的频率并从测试设备接收谐振频率。 谐振频率将被看作是在测试装置处的信号响应的减小。

    Methods and systems involving electrically reprogrammable fuses
    34.
    发明授权
    Methods and systems involving electrically reprogrammable fuses 有权
    涉及电可重新编程保险丝的方法和系统

    公开(公告)号：US08716071B2

    公开(公告)日：2014-05-06

    申请号：US13775570

    申请日：2013-02-25

    Applicant: International Business Machines Corporation

    Inventor： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

    IPC: H01L21/82

    CPC classification number: G11C17/16 ,  H01L21/7682 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

    Abstract translation: 一种电可重新编程的保险丝，其包括设置在电介质材料中的互连，布置在所述互连的第一端的感测线，布置在所述互连的第二端的第一编程线，以及设置在所述互连的第二端的第二编程线 其中当从所述第一编程线通过所述互连件施加第一定向电子线到所述第二编程线时，所述保险丝可操作以在所述互连和感测线之间的界面处形成表面空隙，并且其中，所述保险丝是 当从所述第二编程线通过所述互连件施加第二编程线到所述第一编程线时，还可操作以治愈所述互连和所述感测线之间的表面空隙。

    Self-repair integrated circuit and repair method
    35.
    发明授权
    Self-repair integrated circuit and repair method 有权
    自修复集电路及维修方法

    公开(公告)号：US08687445B2

    公开(公告)日：2014-04-01

    申请号：US13846229

    申请日：2013-03-18

    Applicant: International Business Machines Corporation

    Inventor： Louis L. C. Hsu ,  Rajiv V. Joshi ,  Zhijian J. Yang ,  Ping-Chuan Wang

    IPC: G11C7/00

    CPC classification number: G11C29/04 ,  G11C7/12 ,  G11C11/412

    Abstract: A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.

    Abstract translation: 用于修复劣化场效应晶体管的方法包括场效应晶体管（FET）的源极和漏极之一的正偏置PN结以及FET的主体。 电荷从衬底注入到栅极区域以中和栅极区域中的电荷。 该方法适用于CMOS器件。 公开了用于实施修理的维修电路。

    Clock phase shift detector
    36.
    发明授权
    Clock phase shift detector 有权
    时钟相移检测器

    公开(公告)号：US08669786B1

    公开(公告)日：2014-03-11

    申请号：US13707789

    申请日：2012-12-07

    Applicant: International Business Machines Corporation

    Inventor： Kai D. Feng ,  Jong-ru Guo ,  Trushil N. Shah ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC: G01R25/00

    CPC classification number: H03K5/00 ,  H03L7/087

    Abstract: A clock phase shift detector circuit may include a phase detector that receives a first and a second clock signal, whereby the phase detector generates a phase signal based on a phase difference between the first and the second clock signal. A first integrator is coupled to the phase detector, receives the phase signal, and generates an integrated phase signal. A second integrator receives the first clock signal and generates an integrated first clock signal. A comparator is coupled to the first and the second integrator, whereby the comparator receives the integrated phase signal and the integrated first clock signal. The comparator may then generate a control signal that detects a change between the phase difference of the first and the second clock signal and an optimized phase difference based on an amplitude comparison between the integrated phase signal and the integrated first clock signal.

    Abstract translation: 时钟相移检测器电路可以包括接收第一和第二时钟信号的相位检测器，由此相位检测器基于第一和第二时钟信号之间的相位差产生相位信号。 第一积分器耦合到相位检测器，接收相位信号，并产生积分相位信号。 第二积分器接收第一时钟信号并产生积分的第一时钟信号。 比较器耦合到第一和第二积分器，由此比较器接收积分相位信号和集成的第一时钟信号。 然后，比较器可以产生控制信号，该控制信号基于积分相位信号和集成的第一时钟信号之间的幅度比较来检测第一和第二时钟信号的相位差与优化的相位差之间的变化。

    METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES
    37.
    发明申请
    METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES 有权

    公开(公告)号：US20130176805A1

    公开(公告)日：2013-07-11

    申请号：US13775570

    申请日：2013-02-25

    Applicant: International Business Machines Corporation

    Inventor： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin LI ,  Ping-Chuan Wang

    IPC: G11C17/16

    CPC classification number: G11C17/16 ,  H01L21/7682 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

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