公开(公告)号：US20190341454A1

公开(公告)日：2019-11-07

申请号：US16516803

申请日：2019-07-19

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu

IPC: H01L29/10 ,  H01L21/225 ,  H01L29/06 ,  H01L29/737 ,  H01L29/08 ,  H01L29/66 ,  H01L21/324

Abstract: A device structure for a bipolar junction transistor includes a base layer made of a semiconductor material. An emitter is disposed on a first portion of the base layer. A dopant-containing layer is disposed on a second portion of the base layer. A hardmask is disposed on the base layer. The hardmask includes a window aligned with the second portion of the base layer. Deposits of the dopant-containing layer are limited to exposed surfaces of: the first portion that is disposed on a top surface of the base layer inside of the window.

公开(公告)号：US10211324B2

公开(公告)日：2019-02-19

申请号：US15795884

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Joseph R. Greco ,  Qizhi Liu ,  Aaron L. Vallett ,  Robert F. Vatter

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/10 ,  H01L21/768 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/423 ,  H01L29/45 ,  H01L27/082 ,  H01L21/762 ,  H01L27/06 ,  H01L29/417 ,  H01L21/8249

Abstract: Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

公开(公告)号：US20180069105A1

公开(公告)日：2018-03-08

申请号：US15795884

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Joseph R. Greco ,  Qizhi Liu ,  Aaron L. Vallett ,  Robert F. Vatter

IPC: H01L29/732 ,  H01L29/66 ,  H01L21/768 ,  H01L27/082 ,  H01L29/06 ,  H01L29/45 ,  H01L29/423 ,  H01L29/16 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L27/06 ,  H01L21/8249

CPC classification number: H01L29/732 ,  H01L21/76232 ,  H01L21/76879 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/66287

Abstract: Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

公开(公告)号：US20180068887A1

公开(公告)日：2018-03-08

申请号：US15812320

申请日：2017-11-14

Applicant: International Business Machines Corporation

Inventor： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/306

CPC classification number: H01L21/76289 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0273 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

公开(公告)号：US09799720B2

公开(公告)日：2017-10-24

申请号：US14484536

申请日：2014-09-12

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Qizhi Liu ,  Zhenzhen Ye ,  Yan Zhang

IPC: H01L49/02 ,  H01L21/762 ,  H01L27/02 ,  H01L29/06 ,  H01L23/64 ,  H01L29/786 ,  H01L23/36

CPC classification number: H01L28/10 ,  H01L21/76283 ,  H01L21/764 ,  H01L23/36 ,  H01L23/645 ,  H01L27/0248 ,  H01L29/0649 ,  H01L29/78603 ,  H01L2924/0002 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/00

Abstract: The present invention relates generally to semiconductor structures and methods of manufacturing and, more particularly, to improving heat dissipation of devices, such as active devices like inductors, by filling portions of the semiconductor structure with thermally conductive and electrical isolating material that may serve as a heat sink to a base substrate. In an embodiment, an inductor may be formed above a cavity region in which the thermally conductive and electrical isolating material has been formed. Heat may then be dissipated from the inductor to the cavity, and eventually to the base substrate, through trenches filled with the thermally conductive and electrical isolating material.

公开(公告)号：US09356097B2

公开(公告)日：2016-05-31

申请号：US13926644

申请日：2013-06-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David L. Harame ,  Vikas K. Kaushal ,  Marwan H. Khater ,  Qizhi Liu

IPC: H01L31/0328 ,  H01L29/08 ,  H01L29/66 ,  H01L29/417 ,  H01L29/732 ,  H01L29/737 ,  H01L29/45 ,  H01L29/06

CPC classification number: H01L29/0817 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7378 ,  Y10S148/011

Abstract: Embodiments of the present invention include a method for forming a semiconductor emitter and the resulting structure. The invention comprises forming an epitaxial base layer on a semiconductor substrate. A dielectric layer is deposited over the epitaxial base layer. An opening is etched in a portion of the dielectric layer exposing a portion of the epitaxial base layer and a spacer is deposited along the sidewall of the opening. The emitter is grown from the epitaxial base layer to overlap the top surface of the spacer and a portion of the dielectric layer. The single crystal emitter is formed without a mask and without the requirement of subsequent patterning processes.

Abstract translation: 本发明的实施例包括形成半导体发射器的方法和所得到的结构。 本发明包括在半导体衬底上形成外延基底层。 介电层沉积在外延基底层上。 在电介质层的暴露一部分外延基底层的部分中蚀刻开口，并且间隔物沿着开口的侧壁沉积。 发射极从外延基底层生长以与间隔物的顶表面和电介质层的一部分重叠。 单晶发射体不用掩模形成，不需要后续的图案化工艺。

公开(公告)号：US09349880B2

公开(公告)日：2016-05-24

申请号：US14306373

申请日：2014-06-17

Applicant: International Business Machines Corporation

Inventor： Christopher J. Funch ,  Qizhi Liu ,  Dean W. Siegel

IPC: H01L29/868 ,  H01L29/66 ,  H01L49/02

CPC classification number: H01L29/868 ,  H01L21/76 ,  H01L21/76264 ,  H01L21/764 ,  H01L28/86 ,  H01L28/90 ,  H01L29/0688 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/861

Abstract: Disclosed are semiconductor devices (e.g., diodes, such as PN junction diodes and PIN junction diodes, and capacitors) that have semiconductor bodies with interleaved horizontal portions. In the case of a diode, the semiconductor bodies can have different type conductivities and, optionally, can be separated by an intrinsic semiconductor layer. In the case of a capacitor, the semiconductor bodies can have the same or different type conductivities and can be separated by a dielectric layer. In any case, due to the interleaved horizontal portions, the semiconductor devices each have a relatively large active device region within a relatively small area on an integrated circuit chip. Also disclosed herein are methods of forming such semiconductor devices.

Abstract translation: 公开了具有交错水平部分的半导体本体的半导体器件（例如，二极管，例如PN结二极管和PIN结二极管和电容器）。 在二极管的情况下，半导体主体可以具有不同的类型电导率，并且可选地可以由本征半导体层分离。 在电容器的情况下，半导体主体可以具有相同或不同的类型的电导率，并且可以被介电层分离。 在任何情况下，由于交错的水平部分，半导体器件在集成电路芯片上的相对小的区域内各自具有相对较大的有源器件区域。 本文还公开了形成这种半导体器件的方法。

公开(公告)号：US09324828B2

公开(公告)日：2016-04-26

申请号：US14457524

申请日：2014-08-12

Applicant: International Business Machines Corporation

Inventor： Joseph R. Greco ,  Qizhi Liu ,  Aaron L. Vallett ,  Robert F. Vatter

IPC: H01L21/331 ,  H01L29/66 ,  H01L29/732 ,  H01L29/10 ,  H01L21/768

CPC classification number: H01L29/732 ,  H01L21/76232 ,  H01L21/76879 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/66287

Abstract: Various particular embodiments include a method of amorphizing a portion of silicon underneath the N+ base section of a PNP transistor structure. After amorphizing, the method can include selectively etching that implant-amorphized silicon to trim the collector-base area and collector-base junction. The selective etching is enhanced because the unimplanted silicon region etches at a distinct rate than the implant-amorphized silicon, allowing for control over the trimming of the collector-base junction.

Abstract translation: 各种具体实施例包括使PNP晶体管结构的N +基极部分下方的硅的一部分非晶化的方法。 在非晶化之后，该方法可以包括选择性地蚀刻该植入物非晶化硅以修整集电极 - 基极区域和集电极 - 基极结。 选择性蚀刻被增强，因为未植入的硅区域以与植入物非晶化硅不同的速率蚀刻，允许控制集电极 - 基极结的修整。

公开(公告)号：US20160005775A1

公开(公告)日：2016-01-07

申请号：US14323164

申请日：2014-07-03

Applicant: International Business Machines Corporation

Inventor： John J. Ellis-Monaghan ,  Qizhi Liu ,  Steven M. Shank

IPC: H01L27/146

CPC classification number: H01L27/14632 ,  G02B6/4202 ,  H01L21/76224 ,  H01L21/76283 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/0232 ,  H01L31/02327 ,  H01L31/101

Abstract: Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in the substrate below the first. A photodetector is on the substrate aligned above the first and second trench isolation regions. In another structure, a semiconductor layer is on an insulator layer and laterally surrounded by a first trench isolation region. A second trench isolation region is in and at the top surface of a substrate below the insulator layer and first trench isolation region. A photodetector is on the semiconductor layer and extends laterally onto the first trench isolation region. The stacked trench isolation regions provide sufficient isolation below the photodetector to allow for direct coupling with an off-chip optical fiber.

Abstract translation: 公开了形成结构的结构和方法，以便具有通过堆叠的沟槽隔离区从衬底隔离的光电检测器。 在一种结构中，第一沟槽隔离区位于衬底的顶表面中并且位于衬底的顶表面处，并且第二沟槽隔离区位于第一沟槽下方的衬底中。 光电探测器在衬底上对准在第一和第二沟槽隔离区之上。 在另一种结构中，半导体层位于绝缘体层上并被第一沟槽隔离区横向包围。 第二沟槽隔离区位于绝缘体层和第一沟槽隔离区下面的衬底的顶表面中和在其顶表面。 光电检测器在半导体层上并且横向延伸到第一沟槽隔离区域上。 层叠的沟槽隔离区域在光电检测器下面提供足够的隔离以允许与片外光纤的直接耦合。

公开(公告)号：US20150357447A1

公开(公告)日：2015-12-10

申请号：US14300944

申请日：2014-06-10

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  David L. Harame ,  Michael L. Kerbaugh ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/732 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/732 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7327 ,  H01L29/7371 ,  H01L29/7378

Abstract: The present disclosure relates to integrated circuit (IC) structures and methods of forming the same. An IC structure according to the present disclosure can include: a doped substrate region adjacent to an insulating region; a crystalline base structure including: an intrinsic base region located on and contacting the doped substrate region, the intrinsic base region having a first thickness; an extrinsic base region adjacent to the insulating region, wherein the extrinsic base region has a second thickness greater than the first thickness; a semiconductor layer located on the intrinsic base region of the crystalline base structure; and a doped semiconductor layer located on the semiconductor layer.

Abstract translation: 本公开涉及集成电路（IC）结构及其形成方法。 根据本公开的IC结构可以包括：与绝缘区域相邻的掺杂衬底区域; 晶体基底结构，其包括：位于掺杂衬底区域上并与其接触的本征基极区域，本征基极区域具有第一厚度; 与所述绝缘区域相邻的外部基极区域，其中所述非本征基极区域具有大于所述第一厚度的第二厚度; 位于所述晶体基底结构的本征基极区上的半导体层; 以及位于半导体层上的掺杂半导体层。