公开(公告)号：US20200168698A1

公开(公告)日：2020-05-28

申请号：US16774194

申请日：2020-01-28

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Wei Wang ,  Zheng Xu

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/265 ,  H01L21/324

Abstract: A method of forming an integrated circuit device having a nanosheet resistor includes forming a nanosheet structure having alternating sheets of silicon and silicon germanium. An ion implantation is performed on the nanosheet structure. A thermal anneal is performed on the nanosheet structure. A dielectric oxide is placed around the nanosheet structure. A first contact and a second contact are coupled to the nanosheet structure to form a resistor between the first contact and the second contact. Other embodiments are also described herein.

公开(公告)号：US20200135938A1

公开(公告)日：2020-04-30

申请号：US16675391

申请日：2019-11-06

Applicant: International Business Machines Corporation

Inventor： Dexin Kong ,  Zhenxing Bi ,  Zheng Xu ,  Kangguo Cheng

IPC: H01L29/792 ,  H01L21/28 ,  H01L27/11578 ,  H01L29/06 ,  H01L29/66

Abstract: A integrated device including a non-volatile memory (NVM) and a nanosheet field effect transistor (FET) and a method of fabricating the device include patterning fins for a channel region of the NVM and the FET. The method also includes depositing an organic planarization layer (OPL) and a block mask to protect the fins for the channel region of the FET, conformally depositing a set of layers that make up an NVM structure in conjunction with the channel region of the NVM while protecting the fins for the channel region of the FET with the OPL and the block mask, and removing the OPL and the block mask protecting the fins for the channel region of the FET. Source and drain regions of the NVM and the FET are formed, and a gate of the FET is formed while protecting the NVM by depositing another OPL and another block mask.

公开(公告)号：US20200083382A1

公开(公告)日：2020-03-12

申请号：US16686643

申请日：2019-11-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zheng Xu ,  Zhenxing Bi ,  Dexin Kong ,  Qianwen Chen

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11521 ,  H01L29/06 ,  H01L29/786 ,  H01L29/49

Abstract: A semiconductor device including a gate-all-around based non-volatile memory device includes isolated channels including tunnel dielectric material disposed around gate-all-around field effect transistor (GAA FET) channels, at least one floating gate including a first gate material encapsulating the isolated channels, and at least one control gate including a second gate material encapsulating the isolated channels.

公开(公告)号：US20200082049A1

公开(公告)日：2020-03-12

申请号：US16682413

申请日：2019-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dongbing Shao ,  Zheng Xu ,  Lawrence A. Clevenger

IPC: G06F17/50

Abstract: A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.

公开(公告)号：US20190334477A1

公开(公告)日：2019-10-31

申请号：US15967049

申请日：2018-04-30

Applicant: International Business Machines Corporation

Inventor： Zheng Xu ,  Hung Tran ,  Qianwen Chen ,  Ruqiang Bao

IPC: H03B5/08 ,  H03B1/00 ,  H05K3/30 ,  H05K3/40

Abstract: Techniques for co-tuning of inductance (L) and capacitance (C) in a VNCAP-based LC tank oscillator are provided. In one aspect, an LC tank oscillator includes: a capacitor including at least two metal layers, each metal layer having metal fingers that are interdigitated, wherein an orientation of the metal fingers alternates amongst the at least two metal layers; and an inductor on the capacitor. Inter-layer vias can be present interconnecting the at least two metal layers creating conductive loops between the metal fingers, wherein an arrangement of the inter-layer vias in an area between the at least two metal layers is configured to co-tune both inductance and capacitance in the LC tank oscillator. A method of operating an LC tank oscillator and a method of co-tuning inductance and capacitance in an LC tank oscillator are also provided.

公开(公告)号：US20190319021A1

公开(公告)日：2019-10-17

申请号：US15954819

申请日：2018-04-17

Applicant: International Business Machines Corporation

Inventor： Zheng Xu ,  Chen Zhang ,  Ruqiang Bao ,  Dongbing Shao

IPC: H01L25/00 ,  H01L21/762 ,  H01L25/07 ,  H01L23/00

Abstract: A method for manufacturing a semiconductor device includes forming a first field-effect transistor (FET) on a substrate, the first FET comprising a first plurality of channel regions extending in a first direction, and stacking a second FET on the first FET, the second FET comprising a second plurality of channel regions extending in a second direction perpendicular to the first direction, wherein the first FET comprises a first gate region extending in the second direction across the first plurality of channel regions, and the second FET comprises a second gate region extending in the first direction across the second plurality of channel regions.

公开(公告)号：US20190140053A1

公开(公告)日：2019-05-09

申请号：US16238982

申请日：2019-01-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu ,  Zheng Xu

IPC: H01L29/08 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234

Abstract: A pair of vertical fin field effect transistors (FinFETs) having different gate lengths, includes, a first bottom source/drain on a first region of a substrate, wherein the first bottom source/drain includes a first tier having a first height adjacent to a first vertical fin and a second tier having a second height greater than the first tier removed from the first vertical fin; and a second bottom source/drain on a second region of the substrate, wherein the second bottom source/drain includes a third tier having a third height adjacent to a second vertical fin and a fourth tier having a fourth height greater than the third tier removed from the second vertical fin, wherein the third height is less than the first height and the fourth height is equal to the second height.

公开(公告)号：US20180315755A1

公开(公告)日：2018-11-01

申请号：US15582905

申请日：2017-05-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Choonghyun Lee ,  Zheng Xu

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: Semiconductor devices and methods of forming the same include forming vertical semiconductor channels on a bottom source/drain layer in a first-type region and a second-type region. A gate dielectric layer is formed on sidewalls of the vertical semiconductor channels. A first-type work function layer is formed in the first-type region. A second-type work function layer is formed in both the first-type region and the second-type region. A thickness matching layer is formed in the second-type region such that a stack of layers in the first-type region has a same thickness as a stack of layers in the second-type region. Top source/drain regions are formed on a top portion of the vertical channels.

公开(公告)号：US20180220912A1

公开(公告)日：2018-08-09

申请号：US15803210

申请日：2017-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qianwen Chen ,  Huan Hu ,  Zheng Xu ,  Xin Zhang

IPC: A61B5/0408 ,  A61B5/0492 ,  A61B5/0496 ,  A61B5/0478 ,  A61B5/00

CPC classification number: A61B5/0408 ,  A61B5/0478 ,  A61B5/0492 ,  A61B5/0496 ,  A61B5/685 ,  A61B2562/0209 ,  A61B2562/0285 ,  A61B2562/125

Abstract: A method is presented for forming a nanowire electrode. The method includes forming a plurality of nanowires over a first substrate, depositing a conducting layer over the plurality of nanowires, forming solder bumps and electrical interconnections over a second flexible substrate, and integrating nanowire electrode arrays to the second flexible substrate. The plurality of nanowires are silicon (Si) nanowires, the Si nanowires used as probes to penetrate skin of a subject to achieve electrical biopotential signals. The plurality of nanowires are formed over the first substrate by metal-assisted chemical etching.

公开(公告)号：US20180083093A1

公开(公告)日：2018-03-22

申请号：US15477351

申请日：2017-04-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Dongbing Shao ,  Zheng Xu

IPC: H01L49/02

CPC classification number: H01L28/92 ,  H01L28/40 ,  H01L28/60

Abstract: A capacitive device includes a first electrode comprising a nanosheet stack and a second electrode comprising a nanosheet stack, the second electrode arranged substantially parallel to the first electrode. A first conductive contact is arranged on a basal end of the first electrode, and a second conductive contact is arranged on a basal end of the second electrode.