公开(公告)号：US10312237B2

公开(公告)日：2019-06-04

申请号：US16058173

申请日：2018-08-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Choonghyun Lee ,  Zheng Xu

IPC: H01L27/06 ,  H01L27/24 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/786 ,  H01L21/8228 ,  H01L21/8234 ,  H01L21/8238

Abstract: Integrated chips include a first semiconductor device and a second semiconductor device. The first semiconductor device includes a semiconductor channel, a first-type work function layer formed from a first material on the semiconductor channel, and a second-type work function layer formed from a second material on the first-type work function later layer. The second semiconductor device includes a semiconductor channel, a second-type work function layer formed the second material on the semiconductor channel, and a thickness matching layer formed on the second-type work function layer of the second semiconductor device, the thickness matching layer having a thickness roughly equal to a thickness of the first-type work function layer.

公开(公告)号：US10263100B1

公开(公告)日：2019-04-16

申请号：US15924799

申请日：2018-03-19

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistor device. The fabrication operations include forming a sacrificial nanosheet and a channel nanosheet over a substrate, forming a diffusion barrier layer between the sacrificial nanosheet and the channel nanosheet, wherein a diffusion coefficient of the diffusion barrier layer is selected to substantially prevent a predetermined semiconductor material from diffusing through the diffusion barrier layer.

公开(公告)号：US20190096669A1

公开(公告)日：2019-03-28

申请号：US15715559

申请日：2017-09-26

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Thamarai S. Devarajan ,  Nicolas J. Loubet ,  Binglin Miao ,  Muthumanickam Sankarapandian ,  Charan V. Surisetty ,  Chun W. Yeung ,  Jingyun Zhang

IPC: H01L21/02

Abstract: A method for forming a nanosheet semiconductor device includes forming a nanosheet stack comprising channel nanosheets. The method includes depositing silicon on the nanosheet stack, the silicon completely filling a space between adjacent channel nanosheets. The method includes etching the silicon. The method includes exposing the nanosheet stack to a gas phase heat treatment.

公开(公告)号：US10236346B1

公开(公告)日：2019-03-19

申请号：US15793195

申请日：2017-10-25

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu ,  Chen Zhang

IPC: H01L29/10 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example method includes forming a fin channel over a bottom source-or-drain (S/D) region, wherein the fin channel includes an upper fin channel region and a lower fin channel region, and wherein the bottom S/D region includes an upper S/D region and a lower S/D region. The method further includes forming a S/D junction at an interface between the lower fin channel region and the upper S/D region. A doping process is applied. The doping process is configured to drive a first type of dopant into the upper fin channel region.

公开(公告)号：US10236290B2

公开(公告)日：2019-03-19

申请号：US15795753

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L27/08 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/02

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a first source/drain disposed in contact with a substrate. A second source/drain is disposed above the first source/drain. At least one fin structure is disposed between and in contact with the first source/drain and the second source/drain. A width of the first source/drain and the second source/drain gradually decreases towards the fin structure. The method includes forming an oxide in contact with an exposed portion of at least one fin structure. During formation of the oxide, different areas of the exposed fin structure portion are oxidized at different rates. This forms a first region and a second region of the exposed fin structure portion. These regions each have a width that is greater than a width of a third region of the exposed fin structure portion situated between the first and second regions.

公开(公告)号：US10211288B1

公开(公告)日：2019-02-19

申请号：US15789549

申请日：2017-10-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu ,  Zheng Xu

IPC: H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

Abstract: A pair of vertical fin field effect transistors (FinFETs) having different gate lengths, includes, a first bottom source/drain on a first region of a substrate, wherein the first bottom source/drain includes a first tier having a first height adjacent to a first vertical fin and a second tier having a second height greater than the first tier removed from the first vertical fin; and a second bottom source/drain on a second region of the substrate, wherein the second bottom source/drain includes a third tier having a third height adjacent to a second vertical fin and a fourth tier having a fourth height greater than the third tier removed from the second vertical fin, wherein the third height is less than the first height and the fourth height is equal to the second height.

公开(公告)号：US10170640B2

公开(公告)日：2019-01-01

申请号：US15846520

申请日：2017-12-19

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Kangguo Cheng ,  Zheng Xu

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures that reduce shallow trench isolation (STI) undercutting, floating gates, and gate voids without degrading epitaxy quality. The method includes forming a first and second semiconductor fin on a substrate. A buffer layer is formed on a surface of the substrate between the first and second semiconductor fins and a semiconducting layer is formed on the buffer layer. The buffer layer is selectively removed and replaced with a dielectric layer. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a second channel region of the first semiconductor fin. Source and drain epitaxy regions are selectively formed on surfaces of the first gate.

公开(公告)号：US10157923B2

公开(公告)日：2018-12-18

申请号：US15806759

申请日：2017-11-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Choonghyun Lee ,  Zheng Xu

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8228 ,  H01L21/8234 ,  H01L29/786 ,  H01L27/24 ,  H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: Methods of forming semiconductor devices include forming vertical semiconductor channels on a bottom source/drain layer in a first-type region and a second-type region. A gate dielectric layer is formed on sidewalls of the vertical semiconductor channels. A first-type work function layer is formed in the first-type region. A second-type work function layer is formed in both the first-type region and the second-type region. A thickness matching layer is formed in the second-type region such that a stack of layers in the first-type region has a same thickness as a stack of layers in the second-type region. Top source/drain regions are formed on a top portion of the vertical channels.

公开(公告)号：US20180350811A1

公开(公告)日：2018-12-06

申请号：US16058173

申请日：2018-08-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Choonghyun Lee ,  Zheng Xu

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/82285 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0652 ,  H01L27/0658 ,  H01L27/0664 ,  H01L27/2454 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7827 ,  H01L29/78642

Abstract: Integrated chips include a first semiconductor device and a second semiconductor device. The first semiconductor device includes a semiconductor channel, a first-type work function layer formed from a first material on the semiconductor channel, and a second-type work function layer formed from a second material on the first-type work function later layer. The second semiconductor device includes a semiconductor channel, a second-type work function layer formed the second material on the semiconductor channel, and a thickness matching layer formed on the second-type work function layer of the second semiconductor device, the thickness matching layer having a thickness roughly equal to a thickness of the first-type work function layer.

公开(公告)号：US20180308764A1

公开(公告)日：2018-10-25

申请号：US15947474

申请日：2018-04-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L21/8234 ,  H01L21/306 ,  H01L21/3065 ,  H01L27/088 ,  H01L21/02 ,  H01L21/225

CPC classification number: H01L21/823487 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of forming vertical fin field effect transistors, including, forming a silicon-germanium cap layer on a substrate, forming at least four vertical fins and silicon-germanium caps from the silicon-germanium cap layer and the substrate, where at least two of the at least four vertical fins is in a first subset and at least two of the at least four vertical fins is in a second subset, forming a silicon-germanium doping layer on the plurality of vertical fins and silicon-germanium caps, removing the silicon-germanium doping layer from the at least two of the at least four vertical fins in the second subset, and removing the silicon-germanium cap from at least one of the at least two vertical fins in the first subset, and at least one of the at least two vertical fins in the second subset.