公开(公告)号：US12034066B2

公开(公告)日：2024-07-09

申请号：US18112249

申请日：2023-02-21

Applicant: Infineon Technologies AG

Inventor： Antonio Vellei ,  Markus Beninger-Bina ,  Matteo Dainese ,  Christian Jaeger ,  Johannes Georg Laven ,  Alexander Philippou ,  Francisco Javier Santos Rodriguez

IPC: H01L23/00 ,  H01L21/033 ,  H01L21/225 ,  H01L21/265 ,  H01L21/324 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/7397 ,  H01L21/0337 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/7396 ,  H01L29/4238

Abstract: A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current.

公开(公告)号：US20230207673A1

公开(公告)日：2023-06-29

申请号：US18112249

申请日：2023-02-21

Applicant: Infineon Technologies AG

Inventor： Antonio Vellei ,  Markus Beninger-Bina ,  Matteo Dainese ,  Christian Jaeger ,  Johannes Georg Laven ,  Alexander Philippou ,  Francisco Javier Santos Rodriguez

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/40 ,  H01L21/033 ,  H01L21/225 ,  H01L21/265 ,  H01L21/324 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0649 ,  H01L29/0615 ,  H01L29/7396 ,  H01L29/407 ,  H01L29/0619 ,  H01L29/0623 ,  H01L21/0337 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/4238

Abstract: A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current.

公开(公告)号：US11581429B2

公开(公告)日：2023-02-14

申请号：US17350505

申请日：2021-06-17

Applicant: Infineon Technologies AG ,  Infineon Technologies Dresden GmbH & Co. KG

Inventor： Matteo Dainese ,  Alexander Philippou ,  Markus Beninger-Bina ,  Ingo Dirnstorfer ,  Erich Griebl ,  Christian Jaeger ,  Johannes Georg Laven ,  Caspar Leendertz ,  Frank Dieter Pfirsch

IPC: H01L29/00 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

Abstract: A power semiconductor switch includes an active cell region with a drift region, an edge termination region, and IGBT cells within the active cell region. Each IGBT cell includes trenches that extend into the drift region and laterally confine mesas. At least one control trench has a control electrode for controlling the load current. At least one dummy trench has a dummy electrode electrically coupled to the control electrode. At least one further trench has a further trench electrode. At least one active mesa is electrically connected to a first load terminal within the active cell region. Each control trench is arranged adjacent to no more than one active mesa. At least one inactive mesa is adjacent to the dummy trench. A cross-trench structure merges each control trench, dummy trench and further trench to each other. The cross-trench structure overlaps at least partially along a vertical direction with the trenches.

公开(公告)号：US11257914B2

公开(公告)日：2022-02-22

申请号：US17066954

申请日：2020-10-09

Applicant: Infineon Technologies AG

Inventor： Vera Van Treek ,  Roman Baburske ,  Christian Jaeger ,  Christian Robert Mueller ,  Franz-Josef Niedernostheide ,  Frank Dieter Pfirsch ,  Alexander Philippou ,  Judith Specht

IPC: H01L29/417 ,  H01L29/06 ,  H01L23/535 ,  H01L23/00 ,  H01L29/739

Abstract: A semiconductor die includes a semiconductor body having first and second active portions. The first active portion includes first source regions. The second active portion includes second source regions. A gate structure extends from a first surface into the semiconductor body and has a longitudinal gate extension along a lateral first direction. A first load pad and the first source regions are electrically connected. A second load pad and the second source regions are electrically connected. A gap laterally separates the first and second load pads. A lateral longitudinal extension of the gap is parallel to the first direction or deviates therefrom by not more than 60 degree. A connection structure electrically connects the first and second load pads. The connection structure is formed in a groove extending from the first surface into the semiconductor body and/or in a wiring layer formed on the first surface.

公开(公告)号：US20210210604A1

公开(公告)日：2021-07-08

申请号：US17208779

申请日：2021-03-22

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Roman Baburske ,  Christian Jaeger ,  Johannes Georg Laven ,  Helmut Maeckel

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/739

Abstract: An power semiconductor device having a barrier region is provided. A power unit cell of the power semiconductor device has at least two trenches that may both extend into the barrier region. The at least two trenches may both have a respective trench electrode coupled to a control terminal of the power semiconductor device. For example, the trench electrodes are structured to reduce the total gate charge of the power semiconductor device. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by the drift region. The barrier region can be electrically floating.

公开(公告)号：US20210043759A1

公开(公告)日：2021-02-11

申请号：US17078620

申请日：2020-10-23

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Markus Beninger-Bina ,  Matteo Dainese ,  Christian Jaeger ,  Johannes Georg Laven ,  Francisco Javier Santos Rodriguez ,  Antonio Vellei ,  Caspar Leendertz ,  Christian Philipp Sandow

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417

Abstract: A power semiconductor device includes an active cell region with a drift region of a first conductivity type, a plurality of IGBT cells arranged within the active cell region, each of the IGBT cells includes at least one trench that extends into the drift, an edge termination region surrounding the active cell region, a transition region arranged between the active cell region and the edge termination region, at least some of the IGBT cells are arranged within or extend into the transition region, a barrier region of a second conductivity type, the barrier region is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells and does not extend into the transition region, and a first load terminal and a second load terminal, the power semiconductor device is configured to conduct a load current along a vertical direction between.

公开(公告)号：US20190319122A1

公开(公告)日：2019-10-17

申请号：US16456191

申请日：2019-06-28

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Christian Jaeger ,  Johannes Georg Laven ,  Max Christian Seifert ,  Antonio Vellei

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/866 ,  H01L29/41

Abstract: A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body coupled to a first load terminal and a second load terminal and comprising a drift region configured to conduct a load current between said terminals. The drift region comprises dopants of a first conductivity type. A source region is arranged in electrical contact with the first load terminal and comprises dopants of the first conductivity type. A channel region comprises dopants of a second conductivity. At least one power unit cell that includes at least one first type trench. The at least one power unit cell further includes a first mesa zone and a second mesa zone of the semiconductor body.

公开(公告)号：US20190198612A1

公开(公告)日：2019-06-27

申请号：US16290477

申请日：2019-03-01

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Anton Mauder

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L29/417 ,  H01L21/311 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L27/12

CPC classification number: H01L29/0649 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/31144 ,  H01L21/76208 ,  H01L21/764 ,  H01L27/0629 ,  H01L27/1207 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7812 ,  H01L29/7813

Abstract: A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.

公开(公告)号：US20180033705A1

公开(公告)日：2018-02-01

申请号：US15657735

申请日：2017-07-24

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Erich Griebl ,  Johannes Georg Laven ,  Maria Cotorogea

IPC: H01L21/66 ,  G01R31/02 ,  G01R31/26 ,  H01L23/522 ,  H01L21/8234

Abstract: A semiconductor device includes a first source wiring substructure connected to a plurality of source doping region portions of a transistor structure, and a second source wiring substructure connected to a plurality of source field electrodes located in a plurality of source field trenches extending into a semiconductor substrate. A contact wiring portion of the first source wiring substructure and a contact wiring portion of the second source wiring substructure are located in a wiring layer of a layer stack located on the semiconductor substrate. The contact wiring portion of the first source wiring substructure and the contact wiring portion of the second source wiring substructure each have a lateral size sufficient for a contact for at least a temporary test measurement. The wiring layer including the contact wiring portions is located closer to the substrate than any ohmic electrical connection between the first and the second source wiring substructures.

公开(公告)号：US20150270369A1

公开(公告)日：2015-09-24

申请号：US14734723

申请日：2015-06-09

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Alexander Philippou ,  Hans-Joachim Schulze ,  Christian Jaeger ,  Roman Baburske ,  Antonio Vellei

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/266 ,  H01L21/265 ,  H01L21/223

CPC classification number: H01L29/66348 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0696 ,  H01L29/6634 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397

Abstract: A method of manufacturing an insulated gate bipolar transistor includes providing trenches extending from a first surface to a layer section in a semiconductor portion, introducing impurities into mesa sections between the trenches, and forming, from the introduced impurities, second portions of doped regions separated from source regions by body regions. The source regions are electrically connected to an emitter electrode. The second portions have a second mean net impurity concentration exceeding at least ten times a first mean net impurity concentration in first portions of the doped layer. The first portions extend from the body regions to the layer section, respectively.

Abstract translation: 制造绝缘栅双极晶体管的方法包括提供从半导体部分中的第一表面延伸到层部分的沟槽，将杂质引入到沟槽之间的台面部分中，并从引入的杂质形成从第二部分分离出的掺杂区域 源区域按身体区域。 源极区域电连接到发射极电极。 第二部分具有超过掺杂层的第一部分中的第一平均净杂质浓度的至少十倍的第二平均净杂质浓度。 第一部分分别从身体区域延伸到层部分。