公开(公告)号：US20220391524A1

公开(公告)日：2022-12-08

申请号：US17340761

申请日：2021-06-07

Applicant: Infineon Technologies AG

Inventor： Ketan Dewan ,  Trevor Bird ,  Simon Cottam ,  Glenn Ashley Farrall ,  Darren Galpin ,  Frank Hellwig ,  Paul Hubbert ,  Dietmar Koenig ,  Shubhendu Mahajan ,  Sandeep Vangipuram

IPC: G06F21/62 ,  G06F21/85 ,  H03M13/09

Abstract: An interconnect including an input couplable to a source, and an encoder coupled to the input. The encoder is configured to: group information that is received from the source via a same channel; size the grouped information to a common width; and apply protection to the sized grouped information.

公开(公告)号：US11227072B2

公开(公告)日：2022-01-18

申请号：US16108505

申请日：2018-08-22

Applicant: Infineon Technologies AG

Inventor： Avni Bildhaiya ,  Viola Rieger ,  Frank Hellwig ,  Alexander Zeh

IPC: G06F21/74 ,  G06F21/55 ,  G06F21/50 ,  G06F21/62 ,  G07C5/08

Abstract: The present disclosure relates to a security device, a system, and a method for securing a control apparatus. The security device includes a data security unit which is configured to secure data, data communication and information, and includes a first security component inside the data security unit to operate in a first operating mode, and at least one first monitoring unit to operate in a high-availability mode which, said first monitoring unit being configured to detect a fault present in the first security component. The high-availability mode is different from the first operating mode. The security device further includes a second security component which is configured to operate in the high-availability mode and to output a first response signal if a fault is detected by the first monitoring, where the high-availability mode is available independently from the first operating mode.

公开(公告)号：US10372630B2

公开(公告)日：2019-08-06

申请号：US15784403

申请日：2017-10-16

Applicant: Infineon Technologies AG

Inventor： Frank Hellwig ,  Glenn Ashley Farrall ,  Gerhard Wirrer

IPC: G06F12/14 ,  G06F12/06 ,  G06F21/62 ,  G06F21/53

Abstract: A memory protector is configured to evaluate access requests referring to a memory address space. The access requests comprise address parameters referring to addresses of the memory address space. The memory protector comprises an address evaluator, an address results combiner, and a data register. The address evaluator is configured to evaluate whether the address parameters refer to address ranges of a set of address ranges and is configured to provide results regarding the address ranges. The address results combiner is configured to combine results provided by the address evaluator depending on access protection groups to which the address ranges are mapped to. The memory protector is configured to provide access grant results based on combinations provided by the address results combiner. The data register is configured to store data concerning the set of address ranges and concerning a mapping of the address ranges to the access protection groups.

公开(公告)号：US10248595B2

公开(公告)日：2019-04-02

申请号：US15673943

申请日：2017-08-10

Applicant: Infineon Technologies AG

Inventor： Frank Hellwig ,  Gerhard Wirrer ,  Glenn Farrall ,  Neil Hastie

IPC: G06F9/48 ,  G06F13/34 ,  G06F9/455

Abstract: An interrupt interface of a central processing unit (CPU) comprises a bus with a plurality of interfaces to various components of the CPU. These components can include a memory that includes instructions to execute operations of a processor component, a plurality of virtual machines (VMs) and a virtual machine monitor (VMM)/hypervisor configured to execute the plurality of VMs. The processor can receive interrupt requests (interrupt) as service requests in parallel, which can be executed by the VMM or any one or more of the plurality of VMs to execute VM applications on a dedicated instance of a guest operating system for a task. The processor can further determine whether to grant an interrupt request to the VMM and the VMs based on predetermined criteria, including a current task priority, a pending interrupt priority, or an interrupt enable, associated with the current status of each of the component.

公开(公告)号：US20190050356A1

公开(公告)日：2019-02-14

申请号：US15673943

申请日：2017-08-10

Applicant: Infineon Technologies AG

Inventor： Frank Hellwig ,  Gerhard Wirrer ,  Glenn Farrall ,  Neil Hastie

IPC: G06F13/34 ,  G06F9/455 ,  G06F9/48

Abstract: An interrupt interface of a central processing unit (CPU) comprises a bus with a plurality of interfaces to various components of the CPU. These components can include a memory that includes instructions to execute operations of a processor component, a plurality of virtual machines (VMs) and a virtual machine monitor (VMM)/hypervisor configured to execute the plurality of VMs. The processor can receive interrupt requests (interrupt) as service requests in parallel, which can be executed by the VMM or any one or more of the plurality of VMs to execute VM applications on a dedicated instance of a guest operating system for a task. The processor can further determine whether to grant an interrupt request to the VMM and the VMs based on predetermined criteria, including a current task priority, a pending interrupt priority, or an interrupt enable, associated with the current status of each of the component.

公开(公告)号：US10061729B2

公开(公告)日：2018-08-28

申请号：US15924934

申请日：2018-03-19

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Joerg Schepers ,  Frank Hellwig

IPC: G06F13/38 ,  G06F13/364 ,  G06F13/40 ,  G06F13/24 ,  G06F15/78 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/24 ,  G06F13/404 ,  G06F13/4282 ,  G06F15/7807

Abstract: A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.

公开(公告)号：US20180039508A1

公开(公告)日：2018-02-08

申请号：US15784528

申请日：2017-10-16

Applicant: Infineon Technologies AG

Inventor： Simon Brewerton ,  Glenn Farrall ,  Neil Hastie ,  Frank Hellwig ,  Richard Knight ,  Antonio Vilela

IPC: G06F9/455 ,  G06F21/71 ,  G06F9/30 ,  G06F21/85 ,  G06F13/28

CPC classification number: G06F9/45558 ,  G06F9/30043 ,  G06F13/28 ,  G06F21/71 ,  G06F21/85 ,  G06F2009/45583 ,  G06F2009/45587

Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

公开(公告)号：US09575912B2

公开(公告)日：2017-02-21

申请号：US14247972

申请日：2014-04-08

Applicant: Infineon Technologies AG

Inventor： Frank Hellwig ,  Simon Cottam ,  Krishnapriya Chakiat Ramamoorthy

IPC: G06F13/00 ,  G06F13/26 ,  G06F13/28

CPC classification number: G06F13/26 ,  G06F13/28 ,  Y02D10/14

Abstract: A service request interrupt router having Interrupt Control Units (ICUs); and an arbitration unit configured to be shared by the ICUs to arbitrate among Service Request Nodes (SRNs) that have respective service request interrupt signals and that are mapped to the ICUs, to determine for each of the ICUs which of the SRNs has a highest priority.

Abstract translation: 具有中断控制单元（ICU）的服务请求中断路由器; 以及仲裁单元，被配置为由所述ICU共享以在具有各自的服务请求中断信号且映射到所述ICU的服务请求节点（SRN）之间进行仲裁，以针对每个所述ICU确定所述SRN中哪一个具有最高优先级 。

公开(公告)号：US20150089175A1

公开(公告)日：2015-03-26

申请号：US14494078

申请日：2014-09-23

Applicant: Infineon Technologies AG

Inventor： Frank Hellwig ,  Simon Cottam

IPC: G06F12/14 ,  G06F13/28

CPC classification number: G06F12/1458 ,  G06F13/28 ,  G06F2212/1052

Abstract: A bus system includes a functional unit to which a unit identifier is assigned, a memory module for storage of data that has a storage region, and a bus. The functional unit is connected to the memory module via the bus. The storage region is configured such that one or more multiple global authorized identifiers are assigned thereto, so that the functional unit only has reading or writing access to the storage region if the unit identifier assigned to the functional unit corresponds to one of the global authorized identifiers assigned to the storage region.

Abstract translation: 总线系统包括分配有单元标识符的功能单元，用于存储具有存储区域的数据的存储器模块和总线。 功能单元通过总线连接到存储模块。 存储区域被配置为使得一个或多个多个全局授权标识符被分配给其，使得如果分配给功能单元的单元标识符对应于全局授权标识符之一，则功能单元仅对存储区域具有读取或写入访问 分配到存储区域。

公开(公告)号：US20140108869A1

公开(公告)日：2014-04-17

申请号：US13651775

申请日：2012-10-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Simon Brewerton ,  Simon Cottam ,  Frank Hellwig

IPC: G06F11/10

CPC classification number: G06F11/1048

Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.

Abstract translation: 一些实施例涉及直接存储器访问（DMA）控制器。 DMA控制器包括一组事务控制寄存器，用于接收共同描述要由DMA控制器处理的数据传输的事务控制集合的序列。 总线控制器读取和写入存储器，而DMA控制器执行第一事务控制集以完成事务控制集序列中描述的部分数据传输。 完整性检查器基于在执行第一事务控制集期间由DMA控制器实际处理的数据或地址来确定实际的错误检测码。 完整性检查器还基于实际错误检测码是否与包含在事务控制集合的顺序的第二事务控制集中的期望错误检测码相同来选择性地标记错误。