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    Driver circuit for driving electromagnetic actuators
    31.
    发明授权
    Driver circuit for driving electromagnetic actuators 有权

    公开(公告)号：US09989947B2

    公开(公告)日：2018-06-05

    申请号：US13971039

    申请日：2013-08-20

    Applicant: Infineon Technologies AG

    Inventor： Christian Schweikert ,  Juergen Schaefer

    IPC: G05B19/04 ,  F02D41/20 ,  F02D41/28

    CPC classification number: G05B19/04 ,  F02D41/20 ,  F02D41/28 ,  F02D2250/12

    Abstract: Techniques for driving a plurality of inductive actuators are described herein. According to these techniques, a driver unit includes a clock terminal that receives an external clock signal used by an external control unit. The driver unit further includes a serial bus interface configured to communicate with the external control unit via a serial bus. The serial bus is configured to communicate both of trigger commands synchronized to the external clock signal that indicate to at least one of a plurality of programmable control circuits (PCUs) to generate drive signals in response to the trigger commands that are synchronized with the external clock signal and data associated with at least one of the plurality of PCUs and synchronized with the external clock signal, wherein the data is used by the at least one of the plurality of PCUs to generate the drive signals in response to the trigger commands.

    ELECTRONIC DEVICE
    34.
    发明申请
    ELECTRONIC DEVICE 有权

    公开(公告)号：US20220399886A1

    公开(公告)日：2022-12-15

    申请号：US17836181

    申请日：2022-06-09

    Applicant: Infineon Technologies AG

    Inventor： Mihail Jefremow ,  David Zipperstein ,  Juergen Schaefer ,  Holger Dienst ,  Markus Bichl ,  Ralph Mueller-Eschenbach ,  Arndt Voigtlaender

    IPC: H03K17/56 ,  H03M3/00

    Abstract: According to an example, an electronic device includes a component, a supply line providing a supply voltage, a transistor with a control input, a linear first control loop, and a non-linear second control loop. The transistor outputs an output voltage to the component depending on a signal applied to the control input. The linear first control loop includes an ADC to convert an analog output voltage level into a digital measurement signal, a controller to generate a digital control signal for the transistor depending on the digital measurement signal, and a DAC to convert the digital control signal into a first analog control signal. The non-linear second control loop is configured to generate a second analog control signal depending on the analog output voltage level. The second analog control signal is superimposed with the first analog control signal and the combined control signals are fed to the control input of the transistor.

    Fault check without software intervention
    35.
    发明授权
    Fault check without software intervention 有权

    公开(公告)号：US11526389B2

    公开(公告)日：2022-12-13

    申请号：US16891312

    申请日：2020-06-03

    Applicant: Infineon Technologies AG

    Inventor： Ketan Dewan ,  Juergen Schaefer

    IPC: G05B23/02 ,  G06F11/07 ,  G08B21/18 ,  B60W50/02 ,  H04L12/40 ,  B60W50/00

    Abstract: A fault check circuit, including a first channel comparator to output a first channel comparator output signal indicating whether a first channel digital signal is outside of a first channel threshold range, wherein the first channel digital signal is A/D converted from a first channel analog signal; a second channel comparator to output a second channel comparator output signal indicating whether a second channel digital signal is outside of a second channel threshold range, wherein the second channel digital signal is A/D converted from a second channel analog signal; and an alarm generator circuit to combine the first and second channel comparator output signals, and output a fault check signal, wherein the first and second channel comparators and the alarm generator circuit are implemented in hardware, and the fault check circuit performs a fault check without software intervention.

    IMPLEMENTATION TO DETECT FAILURE OR FAULT ON AN ANALOG INPUT PATH FOR SINGLE ANALOG INPUT FUNCTIONAL SAFETY APPLICATIONS
    36.
    发明申请
    IMPLEMENTATION TO DETECT FAILURE OR FAULT ON AN ANALOG INPUT PATH FOR SINGLE ANALOG INPUT FUNCTIONAL SAFETY APPLICATIONS 有权

    公开(公告)号：US20220276323A1

    公开(公告)日：2022-09-01

    申请号：US17739347

    申请日：2022-05-09

    Applicant: Infineon Technologies AG

    Inventor： Ketan Dewan ,  Rocco Calabro ,  Juergen Schaefer

    IPC: G01R31/54 ,  H03M1/12

    Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.

    Data processing device and method for operating a data processing device
    37.
    发明授权
    Data processing device and method for operating a data processing device 有权

    公开(公告)号：US11416301B2

    公开(公告)日：2022-08-16

    申请号：US17167546

    申请日：2021-02-04

    Applicant: Infineon Technologies AG

    Inventor： Konrad Walluszik ,  Juergen Schaefer

    IPC: G06F9/50 ,  G06F9/54

    Abstract: A data processing device is provided. The data processing device includes at least one processor circuit, at least one additional circuit, an accelerator circuit, a first data connection which at least connects the at least one processor circuit to the accelerator circuit and is configured to exchange data between the at least one processor circuit and the accelerator circuit, a second data connection which connects the at least one processor circuit to the at least one additional circuit and is configured to exchange data between the at least one additional circuit and the processor circuit, wherein the first data connection has a higher data rate or a lower latency than the second data connection, and includes an address segment having a first address range, which has at least one first address each for the at least one additional circuit and the accelerator circuit, and a second address range which has at least one second address each for the at least one additional circuit and the accelerator circuit, wherein the data processing device is configured to exchange data using the first data connection when addressing using one of the first addresses, and to exchange data using the second data connection when addressing using one of the second addresses.

    Implementation to detect failure or fault on an analog input path for single analog input functional safety applications
    38.
    发明授权
    Implementation to detect failure or fault on an analog input path for single analog input functional safety applications 有权

    公开(公告)号：US11353517B1

    公开(公告)日：2022-06-07

    申请号：US17114915

    申请日：2020-12-08

    Applicant: Infineon Technologies AG

    Inventor： Ketan Dewan ,  Rocco Calabro ,  Juergen Schaefer

    IPC: G01R31/54 ,  H03M1/12

    Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.

    Pad asymmetry compensation
    40.
    发明授权
    Pad asymmetry compensation 有权

    公开(公告)号：US10305506B2

    公开(公告)日：2019-05-28

    申请号：US15690728

    申请日：2017-08-30

    Applicant: Infineon Technologies AG

    Inventor： Ketan Dewan ,  Reinhard Kussian ,  Juergen Schaefer

    IPC: H03M3/00

    Abstract: A modulator including a delta-sigma modulation circuit having an order greater than 1, and configured to modulate an input signal into a Pulse Density Modulated (PDM) signal; and a Pad Asymmetric Compensation (PAC) circuit configured to linearize a relation between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal, and to output a modified PDM signal, wherein the linearized relation is for compensating for any offset in the PDM signal.

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