公开(公告)号：US20230094032A1

公开(公告)日：2023-03-30

申请号：US18073860

申请日：2022-12-02

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Thomas Basler ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Michael Hell ,  Jens Peter Konrath ,  Shiqin Niu ,  Dethard Peters ,  Konrad Schraml ,  Bernd Leonhard Zippelius

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: A method of producing a silicon carbide (SiC) device includes: forming a stripe-shaped trench gate structure that extends from a first surface of a SiC body into the SiC body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; forming at least one source region of a first conductivity type; and forming a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. Forming the shielding region includes: forming a deep shielding portion; and forming a top shielding portion between the first surface and the deep shielding portion, the top shielding portion being in contact with the first bottom edge.

公开(公告)号：US11552173B2

公开(公告)日：2023-01-10

申请号：US16986338

申请日：2020-08-06

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Thomas Basler ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Michael Hell ,  Jens Peter Konrath ,  Shiqin Niu ,  Dethard Peters ,  Konrad Schraml ,  Bernd Leonhard Zippelius

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: A silicon carbide device includes a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body. The gate structure has a gate length along a lateral first direction. A bottom surface and an active first gate sidewall of the gate structure are connected via a first bottom edge of the gate structure. The silicon carbide device further includes at least one source region of a first conductivity type. A shielding region of a second conductivity type is in contact with the first bottom edge of the gate structure across at least 20% of the gate length.

公开(公告)号：US20190386093A1

公开(公告)日：2019-12-19

申请号：US16431337

申请日：2019-06-04

Applicant: Infineon Technologies AG

Inventor： Frank Dieter Pfirsch ,  Thomas Basler

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/866 ,  H01L29/74 ,  H01L29/739 ,  H01L27/06

Abstract: A power electronic arrangement includes a semiconductor switch structure configured to assume a forward conducting state. A steady-state current carrying capability of the semiconductor switch structure in the forward conducting state is characterized by a nominal current. The semiconductor switch structure is configured to conduct, in the forward conducting state, at least a part of a forward current in a forward current mode of the power electronic arrangement. A diode structure electrically connected in antiparallel to the semiconductor switch structure is configured to conduct at least a part of a reverse current in a reverse mode of the power electronic arrangement. A thyristor structure electrically connected in antiparallel to the semiconductor switch structure has a forward breakover voltage than a diode on-state voltage of the diode structure at a critical diode current value, the critical diode current value amounting to at most five times the nominal current.

公开(公告)号：US10038105B2

公开(公告)日：2018-07-31

申请号：US15229828

申请日：2016-08-05

Applicant: Infineon Technologies AG

Inventor： Thomas Basler ,  Joachim Mahler ,  Hans-Joachim Schulze

IPC: H01L29/861 ,  H01L29/08 ,  H01L29/36 ,  H01L29/45 ,  H01L29/47 ,  H01L29/872 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/861 ,  H01L29/0619 ,  H01L29/08 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/456 ,  H01L29/47 ,  H01L29/7393 ,  H01L29/872

Abstract: A semiconductor device includes at least one highly doped region of an electrical device arrangement formed in a semiconductor substrate and a contact structure including an NTC (negative temperature coefficient of resistance) portion arranged adjacent to the at least one highly doped region at a front side surface of the semiconductor substrate. The NTC portion includes a negative temperature coefficient of resistance material.

公开(公告)号：US09923482B2

公开(公告)日：2018-03-20

申请号：US15214994

申请日：2016-07-20

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Heiko Rettinger ,  Roman Baburske ,  Uwe Jansen ,  Thomas Basler

IPC: H02M3/24 ,  H02M7/44 ,  H02M1/32 ,  H03K5/08

CPC classification number: H02M7/44 ,  H02M1/32 ,  H02M7/487 ,  H02M2001/0048 ,  H03K5/08

Abstract: A system and method for a power inverter with controllable clamps comprises a first voltage swing path, the first voltage swing path including a first plurality of power transistors, the first voltage swing path producing portions of a positive half-wave of an output signal when active; a second voltage swing path, the second voltage swing path including a second plurality of power transistors, the second voltage swing path producing portions of a negative half-wave of the output signal when active; a first clamping component coupled to the first voltage swing path, the first clamping component forming a freewheeling path for the first voltage swing path, the first clamping component comprising a control terminal, the first clamping component having a first stored charge when the control terminal is in a first state and a second stored charge when the control terminal is in a second state, the first stored charge being greater than the second stored charge; and a second clamping component coupled to the second voltage swing path, the second clamping component forming a freewheeling path for the second voltage swing path, the second clamping component comprising a control terminal, the second clamping component having the first stored charge when the control terminal is in the first state and the second stored charge when the control terminal is in the second state.

公开(公告)号：US20160211660A1

公开(公告)日：2016-07-21

申请号：US14975757

申请日：2015-12-19

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Thomas Basler ,  Hans-Joachim Schulze

IPC: H02H3/20 ,  H01L29/06 ,  H01L23/528 ,  H02M3/135 ,  H01L29/423 ,  H01L29/739 ,  H01L27/02 ,  H02M7/44 ,  H01L29/417 ,  H01L29/10

CPC classification number: H02H3/202 ,  H01L23/528 ,  H01L27/0255 ,  H01L27/0825 ,  H01L27/088 ,  H01L29/06 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/78 ,  H01L2924/0002 ,  H02H7/1225 ,  H02M1/00 ,  H02M3/135 ,  H02M7/44 ,  H02M7/48 ,  H01L2924/00

Abstract: A power device includes an active area having at least two switchable regions with different threshold voltages.

Abstract translation: 功率器件包括具有至少两个具有不同阈值电压的可切换区域的有源区。

公开(公告)号：US11929397B2

公开(公告)日：2024-03-12

申请号：US17583324

申请日：2022-01-25

Applicant: Infineon Technologies AG

Inventor： Thomas Basler ,  Caspar Leendertz ,  Hans-Joachim Schulze

IPC: H01L29/08 ,  H01L21/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/32 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/086 ,  H01L21/0465 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/66068 ,  H01L29/7813

Abstract: A semiconductor device includes: a silicon carbide semiconductor body having a source region of a first conductivity type and a body region of a second conductivity type; and a trench structure extending from a first surface into the silicon carbide semiconductor body along a vertical direction, the trench structure having a gate electrode and a gate dielectric. The trench structure is stripe-shaped and runs along a longitudinal direction that is perpendicular to the vertical direction. The source region includes a first source sub-region and a second source sub-region alternately arranged along the longitudinal direction. A doping concentration profile of the first source sub-region along the vertical direction differs from a doping concentration profile of the second source sub-region along the vertical direction. A corresponding method of manufacturing the semiconductor device is also described.

公开(公告)号：US11721689B2

公开(公告)日：2023-08-08

申请号：US17878990

申请日：2022-08-02

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Roman Baburske ,  Thomas Basler ,  Philip Christoph Brandt ,  Maria Cotorogea

IPC: H01L27/02 ,  H01L29/40 ,  H01L29/861 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/739 ,  H03K17/082

CPC classification number: H01L27/0266 ,  H01L27/0255 ,  H01L27/0262 ,  H01L29/0619 ,  H01L29/0684 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/8613 ,  H03K17/0828

Abstract: A semiconductor device includes: a semiconductor region having charge carriers of a first conductivity type; a transistor cell in the semiconductor region; a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type, wherein a transition between the semiconductor channel region and the semiconductor region forms a first pn-junction; a semiconductor auxiliary region in the semiconductor region and having a second doping concentration of charge carriers of the second conductivity type. A transition between the semiconductor auxiliary region and semiconductor region forms a second pn-junction positioned deeper in the semiconductor region as compared to the first pn-junction. The semiconductor auxiliary region is positioned closest to the semiconductor channel region as compared to any other semiconductor region having charge carriers of the second conductivity type and that forms a further pn-junction with the semiconductor region.

公开(公告)号：US11626477B2

公开(公告)日：2023-04-11

申请号：US17375034

申请日：2021-07-14

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Thomas Basler ,  Wolfgang Bergner ,  Rudolf Elpelt ,  Romain Esteve ,  Michael Hell ,  Daniel Kueck ,  Caspar Leendertz ,  Dethard Peters ,  Hans-Joachim Schulze

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.

公开(公告)号：US20220285283A1

公开(公告)日：2022-09-08

申请号：US17752224

申请日：2022-05-24

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ravi Keshav Joshi ,  Ralf Siemieniec ,  Thomas Basler ,  Martin Gruber ,  Jochen Hilsenbeck ,  Dethard Peters ,  Roland Rupp ,  Wolfgang Scholz

IPC: H01L23/532 ,  H01L29/16 ,  H01L21/768 ,  H01L23/00 ,  H01L29/45

Abstract: A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.