公开(公告)号：US20210313744A1

公开(公告)日：2021-10-07

申请号：US17214397

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS

IPC: H01R13/6471 ,  H01R12/73

Abstract: Examples described herein relate to a pin arrangement that includes a first signal pin; a second signal pin; and multiple parallel ground pins positioned between the first and second signal pins. In some examples, the multiple parallel ground pins are coupled to a single pin connector coupled to a first device and a single pin connector coupled to a second device. In some examples, a first leg of the multiple parallel ground pins is positioned parallel to a portion of the first signal pin and wherein a second leg of the multiple parallel ground pins is positioned parallel to a portion of the second signal pin. In some examples, the multiple parallel ground pins provide a 1:N signal to ground ratio for signals transmitted through at least a portion of the first and second signal pins, where N is greater than 1.

公开(公告)号：US20210151916A1

公开(公告)日：2021-05-20

申请号：US17128803

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Xiang LI ,  Konika GANGULY ,  George VERGIS

IPC: H01R12/70 ,  H01R12/71 ,  H01R13/24

Abstract: Connectors with a staggered pin orientation can reduce crosstalk amongst signal pins. In one example, a connector to couple a card or module to a motherboard includes connector housing and a plurality of pins. Each of the plurality of pins includes two ends including a card or module-facing end to couple with the card or module and a motherboard-facing end to couple with the motherboard. Each of the plurality of pins includes a middle section in the connector housing. One or both of the ends include one or more bends relative to the middle section. The plurality of pins includes alternating signal pins and ground pins, wherein the signal pins having an opposite orientation relative to the ground pins.

公开(公告)号：US20200327912A1

公开(公告)日：2020-10-15

申请号：US16911168

申请日：2020-06-24

Applicant: Intel Corporation

Inventor： Xiang LI ,  Phil GENG ,  George VERGIS ,  Mani PRAKASH

IPC: G11C5/04 ,  H05K1/18 ,  H05K3/34 ,  G06F1/18 ,  H05K3/40

Abstract: A connector includes mounting tabs that are extended relative to traditional mounting tabs. On a back side of the printed circuit board (PCB), the mounting tabs connect to a back plate. The mounting tabs extend through the PCB and connect with the back plate, which provides improved structural integrity. Depending on the connector, the use of the mounting tabs can use existing mounting holes for the connector and remove the need for additional mounting holes.

公开(公告)号：US20190296462A1

公开(公告)日：2019-09-26

申请号：US16316586

申请日：2017-07-31

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS

IPC: H01R12/58 ,  H01R12/70 ,  H01R12/57 ,  H01R12/73 ,  H01R13/633 ,  H05K1/14

Abstract: Anchoring power pins are described herein. In one embodiment, a system includes a circuit board including a through hole, and a connector for coupling a module with the circuit board. The connector includes housing including a module-facing side to receive the module and a circuit board-facing side to couple with the circuit board. The connector includes a conductive power pin to both physically anchor the connector to the circuit board and electrically couple the module with the circuit board, the conductive power pin including a tip protruding from the circuit board-facing side of the connector to extend into a matching through hole in the circuit board.

公开(公告)号：US20190213148A1

公开(公告)日：2019-07-11

申请号：US16208224

申请日：2018-12-03

Applicant: Intel Corporation

Inventor： Bill NALE ,  Christopher E. COX ,  Kuljit S. BAINS ,  George VERGIS ,  James A. McCALL ,  Chong J. ZHAO ,  Suneeta SAH ,  Pete D. VOGT ,  John R. GOLES

IPC: G06F13/16 ,  G06F13/40 ,  G11C14/00 ,  G11C11/4096

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C11/4096 ,  G11C14/0009 ,  Y02D10/14 ,  Y02D10/151

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US20190103690A1

公开(公告)日：2019-04-04

申请号：US15721546

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Xiang LI ,  George VERGIS ,  Douglas HEYMANN

IPC: H01R12/73 ,  H01R12/72 ,  H01R12/83 ,  H05K1/02

Abstract: Embodiments include devices, systems, and methods relating to removing heat from a memory module in a connector. One embodiment relates to a memory module connector comprising a first arm, a second arm, and a body portion positioned between the first arm and the second arm, the body portion configured to accept a memory module therein. The memory module connector includes a structure coupled to the first arm and configured to be electrically coupled to a printed circuit board. The memory module connector also includes a heat spreader coupled to the first arm, the heat spreader configured to be brought into thermal contact with a memory module component. Other embodiments are described and claimed.

公开(公告)号：US20180358727A1

公开(公告)日：2018-12-13

申请号：US15622001

申请日：2017-06-13

Applicant: INTEL CORPORATION

Inventor： Xiang LI ,  George VERGIS

IPC: H01R12/72 ,  H01R12/73 ,  H01R43/20

CPC classification number: H01R12/721 ,  H01R12/727 ,  H01R12/737 ,  H01R43/205

Abstract: A surface mount connector includes a housing including inner surfaces surrounding a card edge region, and outer surfaces defining an exterior region. The connector also includes a recess in at least one of the outer surfaces, the recess sized to accept a removably engageable arm therein. The connector also defines a cross-sectional width that is smaller in the recess than at a position adjacent to the recess. Other embodiments are described and claimed.

公开(公告)号：US20180032414A1

公开(公告)日：2018-02-01

申请号：US15728414

申请日：2017-10-09

Applicant: Intel Corporation

Inventor： Mohan J. KUMAR ,  Murugasamy K. NACHIMUTHU ,  George VERGIS

IPC: G06F11/20 ,  G06F11/30 ,  G06F3/06 ,  G06F11/00

Abstract: Embodiments are generally directed to high capacity energy backed memory with off device storage. A memory device includes a circuit board; multiple memory chips that are installed on the circuit board; a controller to provide for backing up contents of the memory chips when a power loss condition is detected; a connection to a backup energy source; and a connection to a backup data storage that is separate from the memory device.

公开(公告)号：US20160379690A1

公开(公告)日：2016-12-29

申请号：US15225717

申请日：2016-08-01

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Klaus RUFF ,  George VERGIS ,  Suneeta SAH

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0787 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1016 ,  G06F11/1612 ,  G06F13/16 ,  G06F13/28 ,  G11C7/1006 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

公开(公告)号：US20250141134A1

公开(公告)日：2025-05-01

申请号：US19004170

申请日：2024-12-27

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS ,  James A. McCALL ,  Yanjie ZHU

IPC: H01R12/72 ,  H01R13/02 ,  H05K1/18

Abstract: A multi-slot connector having reduced DIMM-to-DIMM pitch distances can support up to 64 memory channels for next generation DDR (double data rate) technology, including DDR6. To support the increase in memory channels, while compensating for limited form factor motherboards, the multi-slot connector includes two or more slots for devices, such as DIMMs, to connect to a motherboard or other platform. Reduced pitch distances between the DIMMs, shortened connector pins, thinner contacts, and complementary reduced pitch distances in a ball grid array (BGA) used to connect to the motherboard or other platform, provides a compact multi-slot connector that can support up to 64 memory channels with improved performance characteristics. An optional cooling device can be employed between the slots as needed to maintain optimal performance.