公开(公告)号：US20230093438A1

公开(公告)日：2023-03-23

申请号：US17481266

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Darko GRUJICIC ,  Bai NIE ,  Tarek A. IBRAHIM ,  Ankur AGRAWAL ,  Sandeep GAAN ,  Ravindranath V. MAHAJAN ,  Aleksandar ALEKSOV

IPC: G02B6/12 ,  H04B10/70 ,  G02B6/124 ,  G02B6/13

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises a mold material. In an embodiment, a first photonics integrated circuit (PIC) is within the second layer. In an embodiment, a second PIC is within the second layer, and a waveguide is in the first layer. In an embodiment, the waveguide optically couples the first PIC to the second PIC.

公开(公告)号：US20220278032A1

公开(公告)日：2022-09-01

申请号：US17186289

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Debendra MALLIK ,  Kristof DARMAWIKARTA ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538

Abstract: An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.

公开(公告)号：US20220155539A1

公开(公告)日：2022-05-19

申请号：US16953146

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Brandon C. MARIN ,  Sameer PAITAL ,  Sai VADLAMANI ,  Rahul N. MANEPALLI ,  Xiaoqian LI ,  Suresh V. POTHUKUCHI ,  Sujit SHARAN ,  Arnab SARKAR ,  Omkar KARHADE ,  Nitin DESHPANDE ,  Divya PRATAP ,  Jeremy ECTON ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Zhichao ZHANG ,  Kemal AYGÜN ,  Bai NIE ,  Kristof DARMAWIKARTA ,  James E. JAUSSI ,  Jason M. GAMBA ,  Bryan K. CASPER ,  Gang DUAN ,  Rajesh INTI ,  Mozhgan MANSURI ,  Susheel JADHAV ,  Kenneth BROWN ,  Ankar AGRAWAL ,  Priyanka DOBRIYAL

IPC: G02B6/42

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

公开(公告)号：US20210272881A1

公开(公告)日：2021-09-02

申请号：US17323840

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Aditya S. VAIDYA ,  Ravindranath V. MAHAJAN ,  Digvijay A. RAORANE ,  Paul R. START

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H01L25/065

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

公开(公告)号：US20210125897A1

公开(公告)日：2021-04-29

申请号：US16665621

申请日：2019-10-28

Applicant: Intel Corporation

Inventor： Krishna Vasanth VALAVALA ,  Ravindranath V. MAHAJAN ,  Chandra Mohan JHA

IPC: H01L23/38 ,  H01L23/42 ,  H01L23/367 ,  H01L23/10 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065

Abstract: Embodiments include a semiconductor package with a thermoelectric cooler (TEC), a method to form such semiconductor package, and a semiconductor packaged system. The semiconductor package includes a die with a plurality of backend layers on a package substrate. The backend layers couple the die to the package substrate. The semiconductor package includes the TEC in the backend layers of the die. The TEC includes a plurality of N-type layers, a plurality of P-type layers, and first and second conductive layers. The first conductive layer is directly coupled to outer regions of bottom surfaces of the N-type and P-type layers, and the second conductive layer is directly coupled to inner regions of top surfaces of the N-type and P-type layers. The first conductive layer has a width greater than a width of the second conductive layer. The N-type and P-type layers are directly disposed between the first and second conductive layers.

公开(公告)号：US20210043570A1

公开(公告)日：2021-02-11

申请号：US16534027

申请日：2019-08-07

Applicant: Intel Corporation

Inventor： Sanka GANESAN ,  Kevin MCCARTHY ,  Leigh M. TRIBOLET ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.

公开(公告)号：US20200066640A1

公开(公告)日：2020-02-27

申请号：US15774512

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Arnab SARKAR ,  Ravindranath V. MAHAJAN

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

Abstract: Embodiments are generally directed to hybrid technology 3-D die stacking. An embodiment of an apparatus includes a TSV array substrate including through silicon vias (TSVs) and wire bond contacts; a stack of one or more wire bond dies; and a package coupled with the TSV substrate by a first interconnect, wherein the one or more wire bond dies are connected via one or more wires to one or more wire bond contacts of the TSV array substrate, and wherein the TSV array substrate provides connections to the for each of the one or more wire bond dies.