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46 条记录 (耗时 0.021 秒)

    Differential amplifier with DC offset cancellation
    33.
    发明授权
    Differential amplifier with DC offset cancellation 有权
    具有直流偏移消除的差分放大器

    公开(公告)号：US06914479B1

    公开(公告)日：2005-07-05

    申请号：US10604479

    申请日：2003-07-24

    申请人： Bertrand Gabillard ,  Michel Rivier ,  Fabrice Voisin ,  Philippe Girard

    发明人： Bertrand Gabillard ,  Michel Rivier ,  Fabrice Voisin ,  Philippe Girard

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45475 ,  H03F3/45278 ,  H03F3/45973 ,  H03F2203/45521 ,  H03F2203/45652

    摘要： There is disclosed an improved differential amplifier (20) having a feedback loop that generates an amplified output signal (Vout) from an input signal (Vin) supplied by a preceding stage. It comprises an input matching circuit (11) connected to said preceding stage, a buffer (22) and an amplification section (12) connected in series in the direct amplification line, a first amplifier (16), a RC network (17′) and a second amplifier (23) connected in series in a parallel loop between the outputs and the inputs of the amplification section that generate the feedback signal. The role of said buffer and second amplifier associated in a dedicated direct and feedback signal combining block (21) is to respectively isolate the input signal and the feedback signal from the summing nodes (A′,B′) at the amplification section inputs. As a result, the summation of the input signal and the feedback signal is improved, the DC component of the output signal is filtered out in order to significantly reduce the DC offset. In addition, the input impedance matching represented by parameter S11 is considerably improved.

    摘要翻译： 公开了一种具有反馈回路的改进的差分放大器（20），该反馈回路从由前一级提供的输入信号（Vin）产生放大的输出信号（Vout）。 它包括连接到所述前级的输入匹配电路（11），串联连接在直接放大线路中的缓冲器（22）和放大部分（12），第一放大器（16），RC网络（17'） 以及在产生反馈信号的输出与放大部分的输入之间并联连接的第二放大器（23）。 在专用直接和反馈信号组合块（21）中相关联的所述缓冲器和第二放大器的作用是在放大部分输入端分别隔离来自求和节点（A'，B'）的输入信号和反馈信号。 结果，改善了输入信号和反馈信号的总和，输出信号的直流分量被滤除，以便显着减小直流偏移。 此外，由参数S 11表示的输入阻抗匹配得到显着改善。

    Circuit for testing a semiconductor chip having embedded arrays intermixed with logic
    34.
    发明授权
    Circuit for testing a semiconductor chip having embedded arrays intermixed with logic 失效
    用于测试具有与逻辑混合的嵌入式阵列的半导体芯片的电路

    公开(公告)号：US5717696A

    公开(公告)日：1998-02-10

    申请号：US391997

    申请日：1995-02-21

    申请人： Bertrand Gabillard ,  Michel Rivier

    发明人： Bertrand Gabillard ,  Michel Rivier

    IPC分类号： G01R31/28 ,  G01R31/30 ,  G11C29/00 ,  G11C29/02 ,  G11C29/50 ,  G11C29/56 ,  H01L21/66 ,  H05K10/00

    CPC分类号： G11C29/50 ,  G01R31/3004

    摘要： A test circuit applicable to chips having embedded arrays intermixed with logic is described. Depending on a control signal, the test circuit connects or isolates the arrays to and from the logic. The test circuit operates as a switch placed between the power supply rail of the logic and the power supply rail of the arrays. All input gates are cross-connected to the power supply rail of the logic, and each output gate is connected to the corresponding power supply rail of the arrays. During TEST mode, the control signal turns off the test circuit, cutting off the arrays. The logic is tested while the memory cells remain unselected. Faulty chips are rejected. When the value of the control signal is inverted, a control gate connects all the power supply rails of the arrays to the power supply rail of the logic. The test sequence for the embedded array is then applied. Faulty memory cells are replaced with repairable ones; otherwise, the faulty chips are rejected. Thus, the manufacturing yield of the mixed chips is improved.

    摘要翻译： 描述了适用于具有与逻辑混合的嵌入式阵列的芯片的测试电路。 根据控制信号，测试电路将阵列与逻辑电路连接或隔离。 测试电路用作逻辑电源轨和阵列的电源轨之间的开关。 所有输入门都与逻辑电源轨交叉连接，每个输出门连接到阵列的相应电源轨。 在TEST模式下，控制信号关闭测试电路，切断阵列。 当存储器单元保持未选择时，该逻辑被测试。 错误的芯片被拒绝。 当控制信号的值反转时，控制栅将阵列的所有电源轨连接到逻辑电源轨。 然后应用嵌入式阵列的测试序列。 故障记忆单元被可修复的单元替换; 否则，故障芯片被拒绝。 因此，混合芯片的制造成品率提高。

    Slip-casting system
    35.
    发明授权
    Slip-casting system 失效
    滑移系统

    公开(公告)号：US4338272A

    公开(公告)日：1982-07-06

    申请号：US2736

    申请日：1979-01-11

    申请人： Arthur D. Pelton ,  Michel Rivier

    发明人： Arthur D. Pelton ,  Michel Rivier

    IPC分类号： B28B1/26 ,  B29C41/16 ,  B29C1/02

    CPC分类号： B28B1/262 ,  B29C41/16

    摘要： A slip-casting system utilizing a ceramic powder for the mold. The system facilitates casting thin-walled and/or long objects without additives for demolding.

    摘要翻译： 一种使用陶瓷粉末进行模具的浇注铸造系统。 该系统有助于铸造薄壁和/或长物体，而不需要用于脱模的添加剂。