公开(公告)号：US08367498B2

公开(公告)日：2013-02-05

申请号：US12906820

申请日：2010-10-18

Applicant: Chih-Hao Chang ,  Jeff J. Xu

Inventor： Chih-Hao Chang ,  Jeff J. Xu

IPC: H01L27/12 ,  H01L21/336

CPC classification number: H01L27/0886 ,  H01L27/12 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a fin structure over the semiconductor substrate, the fin structure including a first material portion over the semiconductor substrate and a second material portion over the first material portion; forming a gate structure over a portion of the fin structure, such that the gate structure traverses the fin structure, thereby separating a source region and a drain region of the fin structure, wherein the source and drain regions of the fin structure define a channel therebetween; removing the second material portion from the source and drain regions of the fin structure; and after removing the second material portion, forming a third material portion in the source and drain regions of the fin structure.

公开(公告)号：US20130017660A1

公开(公告)日：2013-01-17

申请号：US13183043

申请日：2011-07-14

Applicant: Ziwei Fang ,  Ying Zhang ,  Jeff J. Xu

Inventor： Ziwei Fang ,  Ying Zhang ,  Jeff J. Xu

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L21/30617 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. In an example, the method includes forming a gate structure over a substrate; forming a doped region in the substrate; performing a first etching process to remove the doped region and form a trench in the substrate; and performing a second etching process that modifies the trench by removing portions of the substrate.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 在一个示例中，该方法包括在衬底上形成栅极结构; 在衬底中形成掺杂区域; 执行第一蚀刻工艺以去除掺杂区域并在衬底中形成沟槽; 以及执行通过去除衬底的部分来修改沟槽的第二蚀刻工艺。

公开(公告)号：US08053299B2

公开(公告)日：2011-11-08

申请号：US12425854

申请日：2009-04-17

Applicant: Jeff J. Xu

Inventor： Jeff J. Xu

IPC: H01L29/78

CPC classification number: H01L29/66795

Abstract: The present disclosure provides a FinFET element and method of fabricating a FinFET element. The FinFET element includes a germanium-FinFET element (e.g., a multi-gate device including a Ge-fin). In one embodiment, the method of fabrication the Ge-FinFET element includes forming silicon fins on a substrate and selectively growing an epitaxial layer including germanium on the silicon fins. A Ge-condensation process may then be used to selectively oxidize the silicon of the Si-fin and transform the Si-fin to a Ge-fin. The method of fabrication provided may allow use of SOI substrate or bulk silicon substrates, and CMOS-compatible processes to form the Ge-FinFET element.

Abstract translation: 本公开提供了FinFET元件和制造FinFET元件的方法。 FinFET元件包括锗-FnFET元件（例如，包括Ge鳍的多栅极器件）。 在一个实施例中，制造Ge-FinFET元件的方法包括在衬底上形成硅散热片，并在硅片上选择性地生长包括锗的外延层。 然后可以使用Ge缩合过程来选择性地氧化Si鳍的硅并将Si鳍转化为Ge鳍。 提供的制造方法可以允许使用SOI衬底或体硅衬底以及CMOS兼容工艺来形成Ge-FinFET元件。

公开(公告)号：US07939353B1

公开(公告)日：2011-05-10

申请号：US12892254

申请日：2010-09-28

Applicant: Jeff J. Xu

Inventor： Jeff J. Xu

IPC: H01L21/00

CPC classification number: H01L21/2822 ,  H01L21/28185 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of forming an integrated circuit includes forming a fluorine-passivated surface of a substrate. A device quality silicon oxide layer is formed by causing the fluorine-passivated surface to interact with an oxygen-containing gas. Hydroxyl groups are substantially formed on a surface of the device quality silicon oxide layer. A high dielectric constant (high-k) gate dielectric layer is formed on the surface of the device quality silicon oxide layer.

Abstract translation: 形成集成电路的方法包括形成基板的氟钝化表面。 通过使氟钝化表面与含氧气体相互作用形成器件质量的氧化硅层。 羟基基本上形成在器件质量的氧化硅层的表面上。 在器件质量的氧化硅层的表面上形成高介电常数（高k）栅介质层。

公开(公告)号：US20110101421A1

公开(公告)日：2011-05-05

申请号：US12784207

申请日：2010-05-20

Applicant: Jeff J. Xu

Inventor： Jeff J. Xu

IPC: H01L29/04 ,  H01L21/20

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L29/045 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/20 ,  H01L29/32 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a trench in the substrate, where a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation, and epitaxially (epi) growing a semiconductor material in the trench. The epi process utilizes an etch component. A first growth rate on the first crystal plane orientation is different from a second growth rate on the second crystal plane orientation.

Abstract translation: 本公开提供一种制造半导体器件的方法，其包括提供半导体衬底，在衬底中形成沟槽，其中沟槽的底表面具有第一晶面取向，并且沟槽的侧表面具有第二晶体面 取向和外延（epi））在沟槽中生长半导体材料。 epi工艺利用蚀刻部件。 第一晶面取向上的第一生长速率与第二晶面取向上的第二生长速率不同。

公开(公告)号：US07915112B2

公开(公告)日：2011-03-29

申请号：US12236115

申请日：2008-09-23

Applicant: Jeff J. Xu ,  Clement H. Wann ,  Chi Chieh Yeh ,  Chi-Sheng Chang

Inventor： Jeff J. Xu ,  Clement H. Wann ,  Chi Chieh Yeh ,  Chi-Sheng Chang

IPC: H01L21/8238

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film.

Abstract translation: CMOS FinFET半导体器件提供了一种NMOS FinFET器件，其包括半导体鳍片上的压应力金属栅极层和包括半导体鳍片上的拉应力金属栅极层的PMOS FinFET器件。 其形成方法包括选择性退火工艺，其选择性地将形成在PMOS器件上的压电金属栅极膜转换为拉伸应力金属栅极膜。

公开(公告)号：US07862962B2

公开(公告)日：2011-01-04

申请号：US12356405

申请日：2009-01-20

Applicant: Ming-Feng Shieh ,  Shinn-Sheng Yu ,  Anthony Yen ,  Shao-Ming Yu ,  Chang-Yun Chang ,  Jeff J. Xu ,  Clement Hsingjen Wann

Inventor： Ming-Feng Shieh ,  Shinn-Sheng Yu ,  Anthony Yen ,  Shao-Ming Yu ,  Chang-Yun Chang ,  Jeff J. Xu ,  Clement Hsingjen Wann

IPC: G03F9/00 ,  G03C5/00

CPC classification number: H01L27/0203 ,  G03F1/00 ,  G03F1/36 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/66795

Abstract: Provided is a method including layout design of an integrated circuit. A first pattern is provided. The first pattern includes an array of dummy line features and a plurality of spacer elements abutting the dummy line features. A second pattern is provided. The second pattern defines an active region of an integrated circuit device. An edge spacer element of the active region is determined. A dummy line feature of the array of dummy line features is biased (e.g., increased in width), the dummy line feature is adjacent an edge spacer element.

Abstract translation: 提供了一种包括集成电路的布局设计的方法。 提供了第一种模式。 第一图案包括虚线特征的阵列和与虚线特征相邻的多个间隔元件。 提供了第二种模式。 第二图案定义了集成电路器件的有源区。 确定有源区的边缘间隔元件。 假线特征阵列的虚线特征被偏置（例如，宽度增加），虚线特征与边缘间隔元件相邻。

公开(公告)号：US08999794B2

公开(公告)日：2015-04-07

申请号：US13183043

申请日：2011-07-14

Applicant: Ziwei Fang ,  Ying Zhang ,  Jeff J. Xu

Inventor： Ziwei Fang ,  Ying Zhang ,  Jeff J. Xu

IPC: H01L21/336 ,  H01L21/306 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/3065

CPC classification number: H01L21/30617 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. In an example, the method includes forming a gate structure over a substrate; forming a doped region in the substrate; performing a first etching process to remove the doped region and form a trench in the substrate; and performing a second etching process that modifies the trench by removing portions of the substrate.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 在一个示例中，该方法包括在衬底上形成栅极结构; 在衬底中形成掺杂区域; 执行第一蚀刻工艺以去除掺杂区域并在衬底中形成沟槽; 以及执行通过去除衬底的部分来修改沟槽的第二蚀刻工艺。

公开(公告)号：US08895426B2

公开(公告)日：2014-11-25

申请号：US12784073

申请日：2010-05-20

Applicant: Jeff J. Xu

Inventor： Jeff J. Xu

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L29/49 ,  H01L27/092 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/49 ,  H01L21/28088 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/78 ,  H01L29/7833 ,  H01L2224/16225

Abstract: A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer.

Abstract translation: 提供了用于形成金属栅极晶体管的最后一种方法。 该方法包括在基底上形成电介质材料内的开口。 栅极电介质结构形成在开口内和衬底上。 工作功能金属层形成在开口内和栅介质结构之上。 在功函数金属层上形成硅化物结构。

公开(公告)号：US08847333B2

公开(公告)日：2014-09-30

申请号：US13224033

申请日：2011-09-01

Applicant: Xiong-Fei Yu ,  Chun-Yuan Chou ,  Da-Yuan Lee ,  Kuang-Yuan Hsu ,  Jeff J. Xu

Inventor： Xiong-Fei Yu ,  Chun-Yuan Chou ,  Da-Yuan Lee ,  Kuang-Yuan Hsu ,  Jeff J. Xu

IPC: H01L29/76 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7848

Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Abstract translation: 公开了一种具有金属栅极的半导体器件。 具有金属栅极的示例性半导体器件包括半导体衬底，半导体衬底上的源极和漏极特征，半导体衬底上的栅极堆叠并且设置在源极和漏极特征之间。 所述栅堆叠包括形成在所述半导体衬底上的HK电介质层，形成在所述HK电介质层的顶部上的金属化合物的多个势垒层，其中每个所述阻挡层具有不同的化学组成; 以及沉积在所述多个阻挡层上的一叠金属栅极层。