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公开(公告)号：US06316800B1
公开(公告)日：2001-11-13
申请号：US09563909
申请日：2000-05-04
IPC分类号： H01L3300
CPC分类号： H01L27/10852 , H01L21/28568 , H01L27/10811 , H01L27/10888 , H01L28/60
摘要： Titanium boride (TiBx), zirconium boride (ZrBx) and hafnium boride (HfBx) barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The barriers protect cell dielectrics from diffusion and other interaction with surrounding materials during subsequent thermal processing.
摘要翻译： 硼化钛（TiBx），硼化锆（ZrBx）和硼化铪（HfBx）屏障和用于集成电路的电池电介质的电极，特别是用于DRAM单元电容器。 在随后的热处理期间，障碍物保护细胞电介质免受扩散和与周围材料的其它相互作用。
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公开(公告)号：US06258729B1
公开(公告)日：2001-07-10
申请号：US09388685
申请日：1999-09-02
IPC分类号： H01L21461
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76802 , H01L21/76877 , H01L28/40 , H01L28/90
摘要： An etching method includes providing a first insulating material layer on a substrate assembly surface and a second insulating material layer on the first insulating material layer. The first insulating material layer has an etch rate that is greater than the etch rate of the second insulating material layer when exposed to an etch composition. Portions of the first insulating material layer and the second insulating material layer are removed using at least the etch composition. Various types of structures (e.g., contacts, capacitors) are formed with use of the method.
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公开(公告)号：US06222222B1
公开(公告)日：2001-04-24
申请号：US09156207
申请日：1998-09-17
IPC分类号： H01L27108
CPC分类号： H01L28/84 , H01L27/10811 , H01L28/91
摘要： Capacitor constructions and methods of forming the same are described. In one implementation, a capacitor container is formed over a substrate and includes an internal surface and an external surface. At least some of the external surface is provided to be rougher than at least some of the internal container surface. A capacitor dielectric layer and an outer capacitor plate layer are formed over at least portions of the internal and the external surfaces of the capacitor container. In another implementation, a layer comprising roughened polysilicon is formed over at least some of the external container surface but not over any of the internal container surface. In a preferred aspect, the roughened external surface or roughened polysilicon comprises hemispherical grain polysilicon.
摘要翻译： 描述了电容器结构及其形成方法。 在一个实施方案中，电容器容器形成在衬底上并且包括内表面和外表面。 至少一些外表面被提供为比内部容器表面中的至少一些更粗糙。 在电容器容器的内表面和外表面的至少一部分上形成电容器介电层和外电容器板层。 在另一个实施方案中，包含粗糙多晶硅的层形成在至少一些外部容器表面上，但不在任何内部容器表面上。 在优选的方面，粗糙化的外表面或粗糙多晶硅包括半球形晶粒多晶硅。
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公开(公告)号：US06949477B2
公开(公告)日：2005-09-27
申请号：US10640309
申请日：2003-08-14
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/314 , H01L21/316 , H01L29/51 , H01L21/31 , H01L21/469
CPC分类号： H01L21/3105 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3144 , H01L21/31604 , H01L29/513 , H01L29/517 , H01L29/518 , Y10S438/901
摘要： A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.
摘要翻译： 制造半导体器件的方法包括沉积电介质膜并使电介质膜在快速热处理室中进行湿氧化。 该技术可以用于例如在集成电路中形成各种元件，包括栅介质膜以及电容元件。 通过RTP工艺提供的紧密温度控制允许快速进行湿氧化，使得氧化物质不会通过电介质膜显着扩散并扩散到下层。 在电容元件的情况下，该技术还可以有助于降低电介质膜的漏电流，而不会显着降低其电容。
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公开(公告)号：US06914017B1
公开(公告)日：2005-07-05
申请号：US09651790
申请日：2000-08-30
IPC分类号： G03F7/20 , H01L21/302
CPC分类号： G03F7/70633 , H01L22/34 , Y10S438/975
摘要： The present invention includes a residue-free overlay target, as well as a method of forming a residue-residue free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers, and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.
摘要翻译： 本发明包括无残留覆盖靶，以及形成无残留覆盖靶的方法。 本发明的无残留覆盖靶由包括一系列凸起线的沟槽或焊盘限定。 包括在本发明的覆盖靶中的突起线基本上消除了覆盖材料层的顶表面处的任何表面形貌，例如凹陷，并且因此防止可能掩盖覆盖靶并阻止进一步加工的工艺残留物的堆积 。 可以使用半导体制造领域中已知的工艺技术来实现和修改本发明的方法，并且包括提供半导体衬底，沉积抗蚀剂层，图案化抗蚀剂，以及执行湿法或干蚀刻以产生至少一个覆盖靶 根据本发明。
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公开(公告)号：US06607953B2
公开(公告)日：2003-08-19
申请号：US10226356
申请日：2002-08-21
申请人： Scott J. DeBoer
发明人： Scott J. DeBoer
IPC分类号： H01L218242
CPC分类号： H01L28/84 , H01L21/3144 , H01L21/31662 , H01L21/3185
摘要： An exemplary embodiment of the present invention discloses a method for forming a storage capacitor for a memory device, by the steps of: forming a bottom electrode of the storage capacitor over a BoroPhosphoSilicate Glass (BPSG) layer; forming a storage capacitor dielectric layer over the bottom electrode, the storage capacitor dielectric layer consisting of a nitride layer that is 50Å or less in thickness; exposing the nitride dielectric layer to heat during a first stage rapid thermal oxidation step at a first temperature range that is equal to or greater than a reflow temperature required to reflow the BPSG layer; exposing the nitride dielectric layer to wet oxidation during a second stage rapid thermal oxidation step, the second stage rapid thermal oxidation step is performed at a second temperature ranging from 810° C. to 1040° C. and for a time duration of less than three minutes and being sufficient to oxidize the nitride dielectric layer to prevent the diffusion of 90% of oxygen atoms through the nitride dielectric layer. The preferred wet oxidation is a steam ambient including a gas selected from the group consisting of O2/HCl, O2/TLC, NO/HCl, NO/TLC, N2O/TLC or O3.
摘要翻译： 本发明的一个示例性实施例公开了一种通过以下步骤形成用于存储器件的存储电容器的方法：在BoroPhospho硅酸盐玻璃（BPSG）层上形成存储电容器的底部电极; 在所述底部电极上形成存储电容器电介质层，所述存储电容器介电层由厚度为50以下的氮化物层组成; 在等于或大于回流所述BPSG层所需的回流温度的第一温度范围的第一阶段快速热氧化步骤期间，使所述氮化物介电层曝光; 在第二阶段快速热氧化步骤期间将氮化物介电层暴露于湿氧化，第二阶段快速热氧化步骤在810℃至1040℃的第二温度下进行，持续时间小于3 分钟，并足以氧化氮化物介电层，以防止90％的氧原子扩散通过氮化物介电层。 优选的湿氧化是包括选自O 2 / HCl，O 2 / TLC，NO / HCl，NO / TLC，N 2 O / TLC或O 3的气体的蒸气环境。
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37.发明授权公开(公告)号：US06566222B2
公开(公告)日：2003-05-20
申请号：US09982294
申请日：2001-10-16
申请人： Scott J. DeBoer
发明人： Scott J. DeBoer
IPC分类号： H04L2120
摘要： Methods of manufacturing capacitor structures with edge zones that are substantially free of hemispherical grain silicon along the upper edges of the capacitor structures are disclosed. The resulting recessed hemispherical grain silicon layers reduce or prevent separation of particles from the hemispherical grain silicon layer during-subsequent manufacturing processes, thereby reducing defects and increasing throughput. Among the methods of the present invention are methods of forming the capacitor structures in which the silicon layer used to form the hemispherical grain silicon is selectively doped. That selective doping provides an edge zone that does not convert to hemispherical grain silicon during manufacturing.
摘要翻译： 公开了沿着电容器结构的上边缘制造基本上不含半球形硅的边缘区的电容器结构的方法。 所产生的凹陷半球形晶粒硅层在随后的制造工艺期间减少或防止颗粒与半球形晶粒硅层分离，从而减少缺陷并提高生产量。 本发明的方法之一是形成电容器结构的方法，其中用于形成半球形晶粒硅的硅层被选择性掺杂。 该选择性掺杂提供了在制造期间不转化为半球形晶粒硅的边缘区域。
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公开(公告)号：US06531728B2
公开(公告)日：2003-03-11
申请号：US09864552
申请日：2001-05-23
IPC分类号： H01L27108
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76802 , H01L21/76877 , H01L28/40 , H01L28/90
摘要： An etching method includes providing a first insulating material layer on a substrate assembly surface and a second insulating material layer on the first insulating material layer. The first insulating material layer has an etch rate that is greater than the etch rate of the second insulating material layer when exposed to an etch composition. Portions of the first insulating material layer and the second insulating material layer are removed using at least the etch composition. Various types of structures (e.g., contacts, capacitors) are formed with use of the method.
摘要翻译： 蚀刻方法包括在第一绝缘材料层上在衬底组装表面上提供第一绝缘材料层和第二绝缘材料层。 当暴露于蚀刻组合物时，第一绝缘材料层具有大于第二绝缘材料层的蚀刻速率的蚀刻速率。 至少使用蚀刻组合物去除第一绝缘材料层和第二绝缘材料层的部分。 使用该方法形成各种类型的结构（例如，触点，电容器）。
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39.发明授权Method of fabricating a semiconductor device with a wet oxidation with steam process 失效用蒸汽工艺制造具有湿氧化的半导体器件的方法公开(公告)号：US07176079B2
公开(公告)日：2007-02-13
申请号：US09912558
申请日：2001-07-26
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/3205 , H01L21/31 , H01L21/469
CPC分类号： H01L21/3105 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3144 , H01L21/31604 , H01L29/513 , H01L29/517 , H01L29/518 , Y10S438/901
摘要： A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.
摘要翻译： 制造半导体器件的方法包括沉积电介质膜并在快速热处理室中对电介质膜进行湿氧化。 该技术可以用于例如在集成电路中形成各种元件，包括栅介质膜以及电容元件。 通过RTP工艺提供的紧密温度控制允许快速进行湿氧化，使得氧化物质不会通过电介质膜显着扩散并扩散到下层。 在电容元件的情况下，该技术还可以有助于降低电介质膜的漏电流，而不会显着降低其电容。
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40.发明授权公开(公告)号：US07092233B2
公开(公告)日：2006-08-15
申请号：US11216411
申请日：2005-08-31
申请人： Scott J. DeBoer , Don C. Powell
发明人： Scott J. DeBoer , Don C. Powell
IPC分类号： H01G4/005
CPC分类号： H01L28/60 , H01L21/7687 , H01L27/10852 , H01L28/91
摘要： An improved capacitor that is less susceptible to the depletion effect and methods for providing the same. The capacitor comprises a first and second electrode and an insulating layer interposed therebetween. The first electrode includes a bulk layer comprising n-doped polysilicon. The first electrode also includes an interface layer extending from a first surface of the bulk layer to the insulating layer. The interface layer is heavily doped with phosphorus so that the depletion region of the first electrode is confined substantially within the interface layer. The method of forming the interface layer comprises depositing a layer of hexamethldisilazane (HMDS) material over the first surface of the bulk layer so that HMDS molecules of the HMDS material chemically bond to the first surface of the bulk layer. The method further comprises annealing the layer of HMDS material in a phosphine ambient so as to replace CH3 methyl groups with PH3 molecules. The interface layer is then passivated in a nitrogen ambient having a reduced temperature so as to reduce the number of dangling silicon bonds of the lower electrode in a manner that results in reduced thermal damage to neighboring circuit elements.
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