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    Semiconductor integrated circuit
    31.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US07569899B2

    公开(公告)日：2009-08-04

    申请号：US11777276

    申请日：2007-07-12

    申请人： Yusuke Kanno ,  Kenichi Yoshizumi

    发明人： Yusuke Kanno ,  Kenichi Yoshizumi

    IPC分类号： H01L27/00

    CPC分类号： H03K19/0016 ,  H01L27/0207 ,  H01L27/11807

    摘要： Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a process common to external input/output circuits I/O. The first power domains include second power domains SPD11 to SPD42 including logic blocks, control circuit blocks SCB1 to SCB4, and thin-film power switches SWN11 to SWN42 that are connected to the thick-film power switches via virtual ground lines VSSM1 to VSSM4, and formed by thin-film power transistors manufactured in a process common to the logic blocks. In this way, power switches having different thickness of gate insulating films from one another are vertically stacked so as to be in a hierarchical structure, and each power switch is individually controlled by a power switch controller and a control circuit block correspondingly to each mode.

    摘要翻译： 逻辑LSI包括第一电源域PD1至PD4，厚膜电源开关SW1至SW4，以及电源开关控制器PSWC1至PSWC4。 厚膜功率开关由在外部输入/输出电路I / O公用的工艺中制造的厚膜功率晶体管形成。 第一电源域包括经由虚拟接地线VSSM1至VSSM4连接到厚膜电源开关的包括逻辑块的第二电源域SPD11至SPD42，控制电路块SCB1至SCB4和薄膜电源开关SWN11至SWN42，以及 由在逻辑块公用的工艺中制造的薄膜功率晶体管形成。 以这种方式，具有彼此不同的栅绝缘膜厚度的电源开关被垂直堆叠以便处于分层结构，并且每个电源开关由对应于每个模式的电源开关控制器和控制电路块分别控制。

    Semiconductor device
    33.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US07126868B2

    公开(公告)日：2006-10-24

    申请号：US11118338

    申请日：2005-05-02

    申请人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

    发明人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

    摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

    Semiconductor device
    34.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20050285659A1

    公开(公告)日：2005-12-29

    申请号：US11202279

    申请日：2005-08-12

    申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Kazumasa Yanagisawa

    发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Kazumasa Yanagisawa

    IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H03K3/356 ,  H03K5/1534 ,  H03K19/0175 ,  H03K19/0185

    CPC分类号： H03K5/1534 ,  H03K3/356113 ,  H03K19/018521

    摘要： A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.

    摘要翻译： 半导体器件包括差分电平转换器电路，其接收第一信号并输出​​更大振幅的第二信号。 差分电平转换器具有用于接收第一信号的第一MISFET对，用于增强第一MISFET对的耐受电压的第二MISFET对以及具有用于锁存来自输出的第二信号的交叉耦合门的第三MISFET对。 使第二MISFET对和第三MISFET对的栅极绝缘膜的膜厚比第一MISFET对的膜厚薄，并且使第一MISFET对和第二MISFET对的阈值电压小于第三MISFET对的阈值电压。 即使在电平转换之前和之后的信号幅度有较大的差异，该电平转换器电路也以高速工作。

    Semiconductor device having pipelined dynamic memory
    36.
    发明授权
    Semiconductor device having pipelined dynamic memory 有权
    具有流水线动态存储器的半导体器件

    公开(公告)号：US06665231B2

    公开(公告)日：2003-12-16

    申请号：US10243664

    申请日：2002-09-16

    申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

    发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

    IPC分类号： G11C800

    CPC分类号： G11C11/406 ,  G11C7/1039 ,  G11C7/1072

    摘要： A dynamic memory requires refreshing to retain data in its memory cells. This may cause access to the dynamic memory for purposes other than refreshing (external access) and access to it for refreshing to compete with each other, resulting in a performance deterioration. According to this invention, a pipelined dynamic memory (PDRAM) is used, and the pipeline frequency (CLK) of the pipelined dynamic memory is made higher than the frequency (CLK1) of external access, and access required for refreshing is made to an unoccupied slot (a timing when any external access request is never issued) in the pipeline of the pipelined dynamic memory. This makes refreshing of the internal dynamic memory an internal operation, which eliminates the need to take refreshing into consideration at the time external access is made, leading to improvement in operating ease and speed.

    摘要翻译： 动态存储器需要刷新以将数据保留在其存储单元中。 这可能导致访问动态存储器用于除了刷新（外部访问）之外的目的，并且访问它以进行刷新以相互竞争，导致性能恶化。 根据本发明，使用流水线动态存储器（PDRAM），并且使流水线动态存储器的流水线频率（CLK）高于外部访问的频率（CLK1），并且将刷新所需的访问设为未占用 时隙（从未发布任何外部访问请求的定时）在流水线动态存储器的流水线中。 这使得内部动态存储器的刷新成为内部操作，这消除了在外部访问时考虑到刷新的需要，从而改善了操作的容易性和速度。

    INFORMATION PROCESSING DEVICE
    38.
    发明申请
    INFORMATION PROCESSING DEVICE 失效
    信息处理设备

    公开(公告)号：US20100083011A1

    公开(公告)日：2010-04-01

    申请号：US12466696

    申请日：2009-05-15

    申请人： Masafumi ONOUCHI ,  Hiroyuki Mizuno ,  Yusuke Kanno ,  Makoto Saen

    发明人： Masafumi ONOUCHI ,  Hiroyuki Mizuno ,  Yusuke Kanno ,  Makoto Saen

    IPC分类号： G06F15/76 ,  G06F1/10 ,  G06F1/26 ,  G06F9/02

    CPC分类号： G06F1/3203 ,  G06F1/10 ,  Y02D10/126

    摘要： In a configuration provided with, for example, sixty four pieces of processor cores, an on-chip-memory, a bus commonly connected thereto, and others, the processor cores are operated by a power supply with low voltage and a clock with low frequency, and the bus is operated by a power supply with high voltage and a clock with high frequency. Each of the processor cores is provided with a bus interface and a frequency divider in order to absorb a power supply voltage difference and a frequency difference between the bus and each of them. The frequency divider generates the clock with low frequency from the clock with high frequency, and the bus interface is provided with a level shifting function, a data width converting function, a hand shaking function between the bus and the bus interface, and the like.

    摘要翻译： 在具有例如六十四个处理器核心，片上存储器，与其连接的总线等的配置中，处理器核心由具有低电压的电源和具有低频率的时钟 ，总线由高电压电源和高频时钟驱动。 每个处理器内核都配有一个总线接口和一个分频器，以便吸收总线与它们中的每一个之间的电源电压差和频率差。 分频器从高频时钟产生低频时钟，总线接口提供电平转换功能，数据宽度转换功能，总线与总线接口之间的手抖功能等。

    SEMICONDUCTOR DEVICE
    40.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20090027984A1

    公开(公告)日：2009-01-29

    申请号：US12242164

    申请日：2008-09-30

    申请人： HIROYUKI MIZUNO ,  Takeshi Sakata ,  Nobuhiro OODAIRA ,  Takao Watanabe ,  Yusuke Kanno

    发明人： HIROYUKI MIZUNO ,  Takeshi Sakata ,  Nobuhiro OODAIRA ,  Takao Watanabe ,  Yusuke Kanno

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

    摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to bit line LBL.

    摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到位线LBL的锁存型读出放大器SA。