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31.发明授权公开(公告)号：US08791545B2
公开(公告)日：2014-07-29
申请号：US13560446
申请日：2012-07-27
IPC分类号： H01L21/02
CPC分类号： H01L21/76885 , H01L21/76816 , H01L21/76832 , H01L21/76834 , H01L27/016 , H01L28/20 , H01L28/40
摘要： Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.
摘要翻译： 包括诸如薄膜电阻器或金属 - 绝缘体 - 金属（MIM）电容器的无源元件的互连结构，用于制造包括无源元件的互连结构的方法，以及体现在机器可读介质中的设计结构，用于设计， 制造或测试诸如射频集成电路的集成电路。 电介质层的顶表面相对于电介质层中导电特征的顶表面凹陷。 无源元件形成在介电层的凹入的顶表面上，并且包括与导电特征的顶表面共面或低于导电特征的顶表面的导电材料层。
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公开(公告)号：US08569888B2
公开(公告)日：2013-10-29
申请号：US13114079
申请日：2011-05-24
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76843 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.
摘要翻译： 公开了一种具有导电扩散阻挡层的结构的布线结构和方法，所述导电扩散阻挡层具有较厚的上部和较薄的下部。 较厚的上部位于布线结构和相邻电介质材料之间的接合处。 较厚的上部：（1）最小化金属离子扩散，从而使TDDB; （2）允许在布线结构的顶部实现对于低TDDB最佳的电线宽度与电介质空间宽度比; 和（3）为通孔着陆提供更大的表面积。 较薄的下部：（1）允许在布线结构的其余部分中保持不同的导线宽度与电介质空间宽度比，以平衡其他竞争因素; （2）允许更大的导线截面减小电流密度，从而减少EM; 和（3）避免了布线结构电阻率的增加。
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33.发明申请INTEGRATED CIRCUIT STRUCTURE HAVING AIR-GAP TRENCH ISOLATION AND RELATED DESIGN STRUCTURE 有权具有空气阻隔层分离的集成电路结构及相关设计结构公开(公告)号：US20130256758A1
公开(公告)日：2013-10-03
申请号：US13436045
申请日：2012-03-30
IPC分类号： H01L29/737 , H01L21/764
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/764 , H01L29/737
摘要： A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.
摘要翻译： 形成集成电路结构的方法包括：通过延伸通过浅沟槽隔离（STI）形成通气孔并进入衬底; 在所述通气孔的底部选择性地去除所述衬底的暴露部分以在所述衬底内形成开口，其中所述衬底内的所述开口邻接所述STI的底表面或侧壁中的至少一个; 并密封通气孔以在基底内的开口中形成气隙。
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公开(公告)号：US08445355B2
公开(公告)日：2013-05-21
申请号：US12969004
申请日：2010-12-15
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , Anthony K. Stamper
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , Anthony K. Stamper
IPC分类号： H01L21/20
CPC分类号： H01L28/82 , H01L23/5223 , H01L27/0207 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes.
摘要翻译： 金属绝缘体金属（MIM）电容器和制造MIM电容器的方法。 MIM电容器包括层间绝缘层（ILD）层，其中各孔由多个侧壁限定，并且各自从ILD层的顶表面延伸到第一层间电介质层。 布置在孔的侧壁和ILD层的顶表面上的层叠层包括底部导电电极，顶部导电电极和位于底部和顶部导电电极之间的电容器电介质。
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35.发明申请INTEGRATED SEMICONDUCTOR DEVICES WITH AMORPHOUS SILICON BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE 有权具有非晶硅光束的集成半导体器件，制造方法和设计结构公开(公告)号：US20130119491A1
公开(公告)日：2013-05-16
申请号：US13294615
申请日：2011-11-11
CPC分类号： H03H9/02007 , G06F17/5072 , H01L21/84 , H01L27/1203 , H03H3/02 , H03H9/1007 , H03H9/173 , H03H2001/0064 , H03H2003/027 , H03H2009/155
摘要： Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS processes, methods of manufacture and design structures are disclosed. The method includes forming at least one beam comprising amorphous silicon material and providing an insulator material over and adjacent to the amorphous silicon beam. The method further includes forming a via through the insulator material and exposing a material underlying the amorphous silicon beam. The method further includes providing a sacrificial material in the via and over the amorphous silicon beam. The method further includes providing a lid on the sacrificial material and over the insulator material. The method further includes venting, through the lid, the sacrificial material and the underlying material to form an upper cavity above the amorphous silicon beam and a lower cavity below the amorphous silicon beam, respectively.
摘要翻译： 公开了与CMOS工艺，制造方法和设计结构集成的体声波滤波器和/或体声波谐振器。 该方法包括形成至少一个包含非晶硅材料的光束并在非晶硅光束上并邻近其提供绝缘体材料。 该方法还包括通过绝缘体材料形成通孔并暴露非晶硅束下面的材料。 该方法还包括在通孔和非晶硅光束上提供牺牲材料。 该方法还包括在牺牲材料上并在绝缘体材料之上提供盖子。 该方法还包括通过盖子排出牺牲材料和下面的材料，以分别在非晶硅束的上方形成上腔，并在非晶硅束的下方形成下腔。
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公开(公告)号：US08440522B2
公开(公告)日：2013-05-14
申请号：US11968686
申请日：2008-01-03
IPC分类号： H01L21/8234 , H01L21/20
CPC分类号： C23C8/02 , C23C8/04 , C23C8/10 , C23C8/24 , C25D11/00 , C25D11/02 , C25D11/026 , H01C7/006 , H01C17/26 , H01L21/263 , H01L27/0802 , H01L29/8605 , Y10S257/904 , Y10S257/914
摘要： A method for increasing an electrical resistance of a resistor that is within a semiconductor structure. A fraction of a surface layer of the resistor is oxidized with oxygen particles. In an embodiment, the fraction of the surface layer is heated by a beam of particles, such that the semiconductor structure is within a chamber that includes the oxygen particles as gaseous oxygen-comprising molecules. In an embodiment, the semiconductor structure is immersed in a chemical solution which includes the oxygen particles, wherein the oxygen particles includes oxygen-comprising liquid molecules, oxygen ions, or an oxygen-comprising gas dissolved in the chemical solution under pressurization. In an embodiment, the resistor is tested to determine whether the electrical resistance of the resistor after being oxidized with the oxygen particles is within a tolerance of a predetermined target resistance.
摘要翻译： 一种用于增加在半导体结构内的电阻器的电阻的方法。 电阻的表面层的一部分被氧颗粒氧化。 在一个实施方案中，表面层的分数由颗粒束加热，使得半导体结构在包含作为气态含氧分子的氧颗粒的室内。 在一个实施方案中，将半导体结构浸入包括氧颗粒的化学溶液中，其中氧颗粒包括在加压下溶解在化学溶液中的含氧液体分子，氧离子或含氧气体。 在一个实施例中，测试电阻器以确定在用氧颗粒氧化后电阻器的电阻是否在预定目标电阻的容限内。
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公开(公告)号：US20130062603A1
公开(公告)日：2013-03-14
申请号：US13231516
申请日：2011-09-13
CPC分类号： B81C99/004
摘要： A test structure for measuring a Micro-Electro-Mechanical System (MEMS) cavity height structure and calibration method. The method includes forming a sacrificial cavity material over a plurality of electrodes and forming an opening into the sacrificial cavity material. The method further includes forming a transparent or substantially transparent material in the opening to form a transparent or substantially transparent window. The method further includes tuning a thickness of the sacrificial cavity material based on measurements obtained through the transparent or substantially transparent window.
摘要翻译： 用于测量微机电系统（MEMS）腔体高度结构和校准方法的测试结构。 该方法包括在多个电极上形成牺牲腔材料并在牺牲腔材料中形成开口。 该方法还包括在开口中形成透明或基本上透明的材料以形成透明或基本上透明的窗口。 该方法还包括基于通过透明或基本上透明的窗口获得的测量值调整牺牲腔材料的厚度。
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公开(公告)号：US08363379B2
公开(公告)日：2013-01-29
申请号：US12858953
申请日：2010-08-18
IPC分类号： H01G5/01
摘要： Embodiments of a method include forming a metal-insulator-metal (MIM) capacitor including a first electrode and a second electrode and an insulator layer between the first and second electrodes, the MIM capacitor also including a reactive layer; and altering the reactive layer to change a capacitive value of the MIM capacitor.
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39.发明授权Device and methodology for reducing effective dielectric constant in semiconductor devices 有权用于降低半导体器件中有效介电常数的器件和方法公开(公告)号：US08343868B2
公开(公告)日：2013-01-01
申请号：US13005201
申请日：2011-01-12
申请人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
发明人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.
摘要翻译： 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越到多个互连的侧壁。
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公开(公告)号：US08299455B2
公开(公告)日：2012-10-30
申请号：US11872291
申请日：2007-10-15
IPC分类号： H01L29/06
CPC分类号： H01L21/28518 , B81B2207/07 , B81C1/00095 , B81C2201/0149 , H01L21/3086 , H01L21/76886 , H01L23/485 , H01L23/5226 , H01L29/41766 , H01L29/665 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
摘要翻译： 自组装聚合物技术用于在存在于半导体结构的导电接触区域中的材料内形成至少一个有序的纳米尺度图案。 具有有序纳米尺寸图案的材料是场效应晶体管的互连结构或半导体源和漏极扩散区的导电材料。 在接触区域内有序的纳米尺寸图案材料的存在增加了用于随后的接触形成的总面积（即界面面积），这又降低了结构的接触电阻。 接触电阻的降低又改善了通过结构的电流的流动。 除了上述之外，本发明的方法和结构不影响结构的结电容，因为结面积保持不变。
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