公开(公告)号：US20090130834A1

公开(公告)日：2009-05-21

申请号：US12188482

申请日：2008-08-08

申请人： Young-Jin Noh ,  Bon-Young Koo ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Chul-Sung Kim ,  Sung-Kweon Baek ,  Jin-Hwa Heo

发明人： Young-Jin Noh ,  Bon-Young Koo ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Chul-Sung Kim ,  Sung-Kweon Baek ,  Jin-Hwa Heo

IPC分类号： H01L21/4763 ,  H01L21/469

CPC分类号： H01L29/42324 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/28273 ,  H01L21/3145 ,  H01L21/31662

摘要： Methods of forming an insulating film include forming an insulating film on a substrate. A first impurity is injected into the insulating film using a thermal process under a first set of processing conditions to form a first impurity concentration peak in a lower portion of the insulating film. A second impurity is injected into the insulating film using the thermal process under a second set of processing conditions, different from the first set of processing conditions, to form a second impurity concentration peak in an upper portion of the insulating film. Injecting the first impurity and injecting the second impurity may be carried out without using plasma and the first impurity concentration peak may be higher than the second impurity concentration peak.

摘要翻译： 形成绝缘膜的方法包括在基板上形成绝缘膜。 使用第一组处理条件下的热处理将第一杂质注入绝缘膜，以在绝缘膜的下部形成第一杂质浓度峰。 在与第一组处理条件不同的第二组处理条件下，使用热处理将第二杂质注入到绝缘膜中，以在绝缘膜的上部形成第二杂质浓度峰。 注入第一杂质并注入第二杂质可以在不使用等离子体的情况下进行，并且第一杂质浓度峰可以高于第二杂质浓度峰。

公开(公告)号：US07510935B2

公开(公告)日：2009-03-31

申请号：US11468944

申请日：2006-08-31

申请人： Sung-Hae Lee ,  Ju-Wan Lim ,  Jae-Young Ahn ,  Sang-Ryol Yang ,  Ki-Hyun Hwang

发明人： Sung-Hae Lee ,  Ju-Wan Lim ,  Jae-Young Ahn ,  Sang-Ryol Yang ,  Ki-Hyun Hwang

IPC分类号： H01L21/8247

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/4234 ,  Y10S438/954

摘要： In an embodiment, a method of manufacturing a charge-trapping dielectric and a silicon-oxide-nitride-oxide-silicon (SONOS)-type non-volatile semiconductor device includes forming the charge-trapping dielectric, and a first oxide layer including silicon oxide. A silicon nitride layer including silicon-rich nitride is formed by a cyclic chemical vapor deposition (CVD) process using a silicon source material and a nitrogen source gas. A second oxide layer is formed on the silicon nitride layer. Hence, the charge-trapping dielectric having good erase characteristics is formed. In the SONOS-type non-volatile semiconductor device including the charge-trapping dielectric, a data erase process may be stably performed.

摘要翻译： 在一个实施例中，制造电荷俘获电介质和氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体器件的方法包括形成电荷俘获电介质和包含氧化硅的第一氧化物层 。 通过使用硅源材料和氮源气体的循环化学气相沉积（CVD）工艺形成包括富含硅的氮化物的氮化硅层。 在氮化硅层上形成第二氧化物层。 因此，形成具有良好擦除特性的电荷俘获电介质。 在包含电荷捕获电介质的SONOS型非易失性半导体器件中，可以稳定地执行数据擦除处理。

公开(公告)号：US20080070368A1

公开(公告)日：2008-03-20

申请号：US11902209

申请日：2007-09-20

申请人： Hong-Suk Kim ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Seung-Jae Baik ,  Sun-Jung Kim ,  Kwang-Min Park ,  In-Sun Yl

发明人： Hong-Suk Kim ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Seung-Jae Baik ,  Sun-Jung Kim ,  Kwang-Min Park ,  In-Sun Yl

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/792 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28282 ,  H01L21/3185 ,  H01L29/4234 ,  H01L29/518 ,  H01L29/7923

摘要： In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.

摘要翻译： 在制造非易失性存储器件的方法中，隧道绝缘层可以形成在衬底的沟道区上。 可以在隧道绝缘层上形成包括氮化硅的电荷俘获层，以从沟道区捕获电子。 可以使用包括氮气的第一气体和包括氧的第二气体来进行热处理，以去除电荷捕获层中的缺陷位点并致密化电荷捕获层。 可以在热处理的电荷俘获层上形成阻挡层，然后可以在阻挡层上形成导电层。 阻挡层，导电层，热处理电荷捕获层和隧道绝缘层可以被图案化以在沟道区上形成栅极结构。 因此，可以提高包括门结构的非易失性存储器件的数据保持性能和/或可靠性。

公开(公告)号：US20070134415A1

公开(公告)日：2007-06-14

申请号：US11563980

申请日：2006-11-28

申请人： Ki-Hyun Hwang ,  U-In Chung ,  Yu-Gyun Shin ,  Jae-Young Ahn ,  Jin-Gyun Kim

发明人： Ki-Hyun Hwang ,  U-In Chung ,  Yu-Gyun Shin ,  Jae-Young Ahn ,  Jin-Gyun Kim

IPC分类号： C23C16/00 ,  B05D3/04 ,  B05D7/00 ,  B05D1/02

CPC分类号： H01L21/02233 ,  H01L21/31654

摘要： An oxidation treatment apparatus for oxidizing a surface of a substrate includes a process chamber for performing a process, a boat supporting the substrate and disposed in the process chamber during the process and a first ozone supply unit supplying ozone to the process chamber. The first ozone supply unit includes an ozone generator disposed at an exterior of the process chamber and an ozone spray nozzle disposed in the process chamber to spray the ozone supplied from the ozone generator into the process chamber.

摘要翻译： 用于氧化基板表面的氧化处理装置包括处理过程的处理室，支撑基板的船，并且在处理过程中设置在处理室中，以及向处理室供应臭氧的第一臭氧供给单元。 第一臭氧供应单元包括设置在处理室外部的臭氧发生器和设置在处理室中的臭氧喷嘴，以将从臭氧发生器供应的臭氧喷射到处理室中。

公开(公告)号：US20050170603A1

公开(公告)日：2005-08-04

申请号：US11024981

申请日：2004-12-30

申请人： Wook Lee ,  In-Seak Hwang ,  Yong-Sun Ko ,  Ki-Hyun Hwang

发明人： Wook Lee ,  In-Seak Hwang ,  Yong-Sun Ko ,  Ki-Hyun Hwang

IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L21/20

CPC分类号： H01L28/84 ,  H01L27/10852 ,  H01L28/91

摘要： A method for forming a capacitor for use in a semiconductor device having electrode plugs surrounded by an insulating film and connected to underlying contact pads, includes sequentially forming an etch stop film and a mold oxide film on the insulating film and the electrode plugs, forming recesses in portions of the mold oxide film and the etching stopper film, the recesses exposing the electrode plugs, forming storage node electrodes in the recesses, filling the recesses in which the storage node electrodes are formed with an artificial oxide film, planarizing the storage node electrodes and the artificial oxide film so that the storage node electrodes are separated from one another, and selectively removing the mold oxide film and the artificial oxide film using a diluted hydrofluoric acid solution containing substantially no ammonium bifluoride.

摘要翻译： 一种用于形成用于半导体器件的电容器的方法，所述半导体器件具有由绝缘膜包围并连接到下面的接触焊盘的电极塞，包括在所述绝缘膜和所述电极插塞上顺序地形成蚀刻停止膜和模制氧化物膜， 在模具氧化膜和蚀刻停止膜的部分中，露出电极塞的凹部，在凹部中形成存储节点电极，用存储节点电极填充形成有人造氧化膜的凹部，使存储节点电极平坦化 和人造氧化物膜，使得储存节点电极彼此分离，并且使用基本上不含氟化二氢铵的稀释的氢氟酸溶液选择性地除去模制氧化物膜和人造氧化物膜。

公开(公告)号：US09698233B2

公开(公告)日：2017-07-04

申请号：US14644408

申请日：2015-03-11

申请人： Eun-Yeoung Choi ,  Young-Jin Noh ,  Bi-O Kim ,  Kwang-Min Park ,  Jae-Young Ahn ,  Ju-Mi Yun ,  Jae-Ho Choi ,  Ki-Hyun Hwang

发明人： Eun-Yeoung Choi ,  Young-Jin Noh ,  Bi-O Kim ,  Kwang-Min Park ,  Jae-Young Ahn ,  Ju-Mi Yun ,  Jae-Ho Choi ,  Ki-Hyun Hwang

IPC分类号： H01L29/792 ,  H01L29/51 ,  H01L27/11582 ,  H01L21/28

CPC分类号： H01L29/513 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/518

摘要： Tunnel insulation layer structures and methods of manufacturing the same are disclosed. The tunnel insulation layer structures may include a first tunnel insulation layer, a second tunnel insulation layer, a third tunnel insulation layer, a fourth tunnel insulation layer and a fifth tunnel insulation layer. The first tunnel insulation layer on a substrate has a first band gap energy. The second tunnel insulation layer on the first tunnel insulation layer has a second band gap energy which is lower than the first band gap energy. The third tunnel insulation layer on the second tunnel insulation layer has a third band gap energy which is higher than the second band gap energy. The fourth tunnel insulation layer on the third tunnel insulation layer has a fourth band gap energy which is lower than the third band gap energy. The fifth tunnel insulation layer on the fourth tunnel insulation layer has a fifth band gap energy which is higher than the fourth band gap energy.

公开(公告)号：US09461061B2

公开(公告)日：2016-10-04

申请号：US14546172

申请日：2014-11-18

申请人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Jin-Gyun Kim ,  Jae-Young Ahn ,  Hun Hyeong Lim ,  Ki-Hyun Hwang

发明人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Jin-Gyun Kim ,  Jae-Young Ahn ,  Hun Hyeong Lim ,  Ki-Hyun Hwang

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.

摘要翻译： 制造垂直存储器件的方法包括在衬底上形成交替和重复的绝缘夹层和牺牲层，牺牲层包括多晶硅或非晶硅，通过绝缘夹层和牺牲层形成通道孔，在通道孔中形成通道， 蚀刻绝缘夹层的部分和相邻通道之间的牺牲层以形成开口，去除牺牲层以在绝缘夹层之间形成间隙，并在间隙中形成栅极线。

公开(公告)号：US20160133643A1

公开(公告)日：2016-05-12

申请号：US14995586

申请日：2016-01-14

申请人： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

发明人： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L21/02

CPC分类号： H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28008 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/7926

摘要： A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.

摘要翻译： 提供半导体器件。 半导体包括在基板上沿第一方向交替堆叠的多个层间绝缘层和多个栅电极。 多个层间绝缘层和多个栅电极构成在第一方向上延伸的侧面。 栅电介质层设置在侧表面上。 沟道图案设置在栅介质层上。 栅介质层包括保护图案，电荷陷阱层和隧穿层。 保护图案包括设置在多个栅电极的对应的栅电极上的部分。 电荷陷阱层设置在保护图案上。 隧道层设置在电荷陷阱层和沟道图案之间。 保护图案比电荷陷阱层更致密。

公开(公告)号：US20150187790A1

公开(公告)日：2015-07-02

申请号：US14643527

申请日：2015-03-10

申请人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

发明人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7889 ,  H01L29/7926

摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.

摘要翻译： 垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。 水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙比第二垂直间隙宽 第一垂直间隙。 水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

公开(公告)号：US08987805B2

公开(公告)日：2015-03-24

申请号：US13971347

申请日：2013-08-20

申请人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

发明人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7889 ,  H01L29/7926

摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.

摘要翻译： 垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。 水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙宽于 第一垂直间隙。 水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。