公开(公告)号：US5751650A

公开(公告)日：1998-05-12

申请号：US724664

申请日：1996-10-01

申请人： Hiroshige Hirano ,  Tetsuji Nakakuma

发明人： Hiroshige Hirano ,  Tetsuji Nakakuma

IPC分类号： G11C5/06 ,  G11C11/22

CPC分类号： G11C11/22 ,  G11C5/063

摘要： In an electric signal supply circuit, a signal generating source and a plurality of circuit cells are connected to each other by a wire line through resistors. Signal wire lines from the signal generating source to the respective circuit cells are formed in the form of a pyramid, and therefore, delay time differences to the circuit cells are reduced. Since delay time differences in a signal to the circuit cells from the signal generating source which is disposed at ends of the plurality of circuit cells are smaller, a circuit operation is stable.

摘要翻译： 在电信号供给电路中，信号发生源和多个电路单元通过电阻线通过有线线连接。 从信号发生源到各个电路单元的信号线以金字塔的形式形成，因此减小了对电路单元的延迟时间差。 由于设置在多个电路单元的端部的来自信号发生源的电路单元的信号的延迟时间差较小，电路操作稳定。

公开(公告)号：US5740114A

公开(公告)日：1998-04-14

申请号：US438919

申请日：1995-05-10

申请人： Hiroshige Hirano ,  Hisakazu Kotani ,  Naomi Miyake

发明人： Hiroshige Hirano ,  Hisakazu Kotani ,  Naomi Miyake

IPC分类号： G11C29/00 ,  G11C29/24 ,  G11C7/00

CPC分类号： G11C29/808 ,  G11C29/24 ,  G11C29/812 ,  G11C29/844

摘要： An apparatus for selecting redundant memory cells in integrated circuit memory devices. The apparatus includes eight memory cell blocks, each of which includes a plurality of memory cell groups, a redundant memory cell group of a first set and a redundant memory cell group of a second set; and eight selecting fuse circuit blocks. Four of the selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the first set of any of the eight memory cell blocks, and the other four selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the second set of any of the eight memory cell blocks.

公开(公告)号：US5546342A

公开(公告)日：1996-08-13

申请号：US322543

申请日：1994-10-13

申请人： George Nakane ,  Toshio Mukunoki ,  Nobuyuki Moriwaki ,  Tatsumi Sumi ,  Hiroshige Hirano ,  Tetsuji Nakakuma

发明人： George Nakane ,  Toshio Mukunoki ,  Nobuyuki Moriwaki ,  Tatsumi Sumi ,  Hiroshige Hirano ,  Tetsuji Nakakuma

IPC分类号： G11C14/00 ,  G11C7/10 ,  G11C11/22 ,  G11C7/00

CPC分类号： G11C7/1006

摘要： The life of a semiconductor memory device can be prolonged by using a plurality of memory cells and decreasing the stress applied to the dielectric film of the memory cells storing a data value "1." This is achieved in the present invention by decreasing the number of rewritings required to retain stored data. Specifically, the present invention utilizes a reverse and rewrite means to reverse and rewrite data back into memory cells after being read, memory means for memorizing a signal indicating whether the currently stored data is in a reversed state, and judging means for judging whether the data should be reversely output.

摘要翻译： 通过使用多个存储单元并减小施加到存储数据值“1”的存储单元的电介质膜的应力，可以延长半导体存储器件的寿命。 这通过减少保留存储数据所需的重写次数在本发明中实现。 具体地，本发明利用反向和重写装置在读取之后将数据反转并重写到存储器单元中，用于存储指示当前存储的数据是否处于反转状态的信号的存储装置，以及用于判断数据 应该反向输出。

公开(公告)号：US08344515B2

公开(公告)日：2013-01-01

申请号：US12782360

申请日：2010-05-18

申请人： Taichi Nishio ,  Hiroshige Hirano ,  Yukitoshi Ota

发明人： Taichi Nishio ,  Hiroshige Hirano ,  Yukitoshi Ota

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a plurality of through vias extending through a substrate. The plurality of through vias are arranged dividedly in three or more via groups. Each of the via groups includes three or more of the through vias that are arranged in two dimensions.

摘要翻译： 半导体器件包括延伸穿过衬底的多个通孔。 多个贯通孔分成三个以上通孔组。 通孔组中的每一个包括三个或更多个以二维排列的通孔。

公开(公告)号：US20120112354A1

公开(公告)日：2012-05-10

申请号：US13289683

申请日：2011-11-04

申请人： Hiroshige Hirano ,  Yukitoshi Ota

发明人： Hiroshige Hirano ,  Yukitoshi Ota

IPC分类号： H01L23/48

CPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first interconnect layer and a second interconnect layer provided above or under the first interconnect layer. The first interconnect layer includes a plurality of first interconnect blocks, and in each of the first interconnect blocks, a first interconnect has a first potential, and extends in at least two or more directions, and a second interconnect has a second potential, and extends in at least two or more directions. The second interconnect layer includes a third interconnect which electrically connects the first interconnect of one of a pair of adjacent first interconnect blocks and the first interconnect of the other of the pair of adjacent first interconnect blocks, and a fourth interconnect which electrically connects the second interconnect of one of the pair of adjacent first interconnect blocks and the second interconnect of the other of the pair of adjacent first interconnect blocks.

摘要翻译： 半导体器件包括设置在第一互连层上方或下方的第一互连层和第二互连层。 第一互连层包括多个第一互连块，并且在每个第一互连块中，第一互连具有第一电位，并且在至少两个或更多个方向上延伸，并且第二互连具有第二电位，并且延伸 在至少两个或更多个方向。 第二互连层包括第三互连，其将一对相邻的第一互连块中的一个的第一互连与该对相邻的第一互连块中的另一个的第一互连电连接，以及将第二互连电连接的第四互连 所述一对相邻的第一互连块中的一个和所述一对相邻的第一互连块中的另一个的所述第二互连。

公开(公告)号：US07184344B2

公开(公告)日：2007-02-27

申请号：US11062826

申请日：2005-02-23

申请人： Tetsuji Nakakuma ,  Hiroshige Hirano

发明人： Tetsuji Nakakuma ,  Hiroshige Hirano

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C11/419 ,  G11C2207/002 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897

摘要： A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one of the following features: the on-state resistance of the column selection switch being higher than that of a transistor array of the differential sense amplifier; separate provision of two column selection switches, one for read operation and the other for write operation; provision of a bit line additional capacitance and a connection control switch therefor; and provision of a data line dividing switch.

摘要翻译： 一种半导体器件包括连接到位线的差分读出放大器，以及数据传输电路，包括用于接通/断开数据线与位线之间的连接的列选择开关。 半导体器件包含以下特征之一：列选择开关的导通电阻高于差分读出放大器的晶体管阵列的导通电阻; 单独提供两个列选择开关，一个用于读操作，另一个用于写操作; 提供位线附加电容及其连接控制开关; 并提供数据线分割开关。

公开(公告)号：US07092275B2

公开(公告)日：2006-08-15

申请号：US11019053

申请日：2004-12-22

申请人： Kunisato Yamaoka ,  Hiroshige Hirano

发明人： Kunisato Yamaoka ,  Hiroshige Hirano

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： In a ferro-electric memory including reference cells, if one reference cell is associated with a plurality of normal cells, a period in which “L” data is written in the reference cell and a period in which “H” data is written or read out in/from the reference cell are controlled to be shorter than a period in which “L” data is written in each normal cell and a period in which “H” data is written or read out in/from each normal cell, respectively. In this manner, stress applied to the reference cell is reduced and, even if writing or reading is repeatedly performed on the normal cells, the reliability of the reference cell is enhanced and deterioration in characteristics of the reference cell due to repetitive rewriting of data is suppressed.

摘要翻译： 在包括参考单元的铁电存储器中，如果一个参考单元与多个正常单元相关联，则将“L”数据写入参考单元的时段和写入或读取“H”数据的周期 被控制为比在每个正常单元中写入“L”数据的时间段和从每个正常单元写入/读出“H”数据的时间段的时间短。 以这种方式，施加到参考单元的应力减小，并且即使对正常单元重复执行写入或读取，参考单元的可靠性增强，并且由于重复的数据重写导致的参考单元的特性的劣化是 被压制

公开(公告)号：US20060145723A1

公开(公告)日：2006-07-06

申请号：US11175450

申请日：2005-07-07

申请人： Hiroshige Hirano

发明人： Hiroshige Hirano

IPC分类号： H03K19/094

CPC分类号： H03K3/356113 ,  H03K17/063 ,  H03K17/102

摘要： A voltage level conversion circuit for converting a voltage level of a low voltage system input signal into a voltage level of a high voltage system signal comprises a latch circuit comprising plural high-breakdown-voltage MOS transistors having a high power supply voltage as a breakdown voltage, a first high-breakdown-voltage N channel MOS transistor which discharges one of latch nodes of the latch circuit, and a second high-breakdown-voltage N channel MOS transistor which discharges the other latch node, and a pulse signal obtained by boosting a low voltage system pulse signal is applied to a gate of the first or second high-breakdown voltage N channel MOS transistor when the input signal transits.

摘要翻译： 用于将低电压系统输入信号的电压电平转换为高电压系统信号的电压电平的电压电平转换电路包括：锁存电路，包括多个具有高电源电压的高击穿电压MOS晶体管作为击穿电压 第一高耐压N沟道MOS晶体管，其对闩锁电路的一个锁存节点进行放电;以及第二高击穿电压N沟道MOS晶体管，其对另一个锁存节点进行放电;以及第二高击穿电压N沟道MOS晶体管， 当输入信号转换时，低电压系统脉冲信号施加到第一或第二高击穿电压N沟道MOS晶体管的栅极。

公开(公告)号：US20050265090A1

公开(公告)日：2005-12-01

申请号：US11121939

申请日：2005-05-05

申请人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

发明人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

IPC分类号： G11C11/22 ,  G11C7/00 ,  G11C29/00 ,  G11C29/12

CPC分类号： G11C29/816 ,  G11C11/22 ,  G11C29/789 ,  G11C2029/4402

摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

摘要翻译： 为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。 半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。 选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

公开(公告)号：US20050141307A1

公开(公告)日：2005-06-30

申请号：US11062826

申请日：2005-02-23

申请人： Tetsuji Nakakuma ,  Hiroshige Hirano

发明人： Tetsuji Nakakuma ,  Hiroshige Hirano

IPC分类号： H01L21/8242 ,  G11C7/06 ,  G11C11/407 ,  G11C11/409 ,  G11C11/419 ,  H01L21/8239 ,  H01L27/105 ,  H01L27/108 ,  G11C11/34

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C11/419 ,  G11C2207/002 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897

摘要： A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one of the following features: the on-state resistance of the column selection switch being higher than that of a transistor array of the differential sense amplifier; separate provision of two column selection switches, one for read operation and the other for write operation; provision of a bit line additional capacitance and a connection control switch therefor; and provision of a data line dividing switch.