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179 条记录 (耗时 0.02 秒)

    Metal High-K Transistor Having Silicon Sidewall for Reduced Parasitic Capacitance, and Process to Fabricate Same
    31.
    发明申请
    Metal High-K Transistor Having Silicon Sidewall for Reduced Parasitic Capacitance, and Process to Fabricate Same 失效
    具有减少寄生电容的硅侧壁的金属高K晶体管及其制造方法

    公开(公告)号：US20090065876A1

    公开(公告)日：2009-03-12

    申请号：US11852359

    申请日：2007-09-10

    申请人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey W. Sleight

    发明人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey W. Sleight

    IPC分类号： H01L29/78 ,  H01L21/3205

    CPC分类号： H01L29/517 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656

    摘要： A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.

    摘要翻译： 公开了一种降低金属高介电常数（MHK）晶体管中的寄生电容的方法。 该方法包括在衬底上形成MHK栅极堆叠，MHK栅极堆叠层具有高介电常数材料的底层，中间金属层和非晶硅或多晶硅之一的顶层。 该方法进一步在MHK栅极堆叠的侧壁上形成耗尽的侧壁层，以覆盖中间层和顶层而不是底层。 耗尽的侧壁层是非晶硅或多晶硅之一。 该方法还在耗尽的侧壁层上方和底层的暴露表面之上形成偏移间隔层。

    Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and performance
    33.
    发明申请
    Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and performance 有权
    用于改善电池稳定性和性能的混合体SOI-6T-SRAM电池

    公开(公告)号：US20060231899A1

    公开(公告)日：2006-10-19

    申请号：US11108012

    申请日：2005-04-15

    申请人： Leland Chang ,  Shreesh Narasimha ,  Norman Rohrer ,  Jeffrey Sleight

    发明人： Leland Chang ,  Shreesh Narasimha ,  Norman Rohrer ,  Jeffrey Sleight

    IPC分类号： H01L29/94

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L27/1207

    摘要： The present invention provides a 6T-SRAM semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.

    摘要翻译： 本发明提供了一种6T-SRAM半导体结构，其包括具有SOI区域和体积-Si区域的衬底，其中SOI区域和体积-Si区域具有相同或不同的晶体取向; 将SOI区域与体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层顶部具有硅层。 体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。 阱接触还用于控制体Si区域中的FET的阈值电压，以优化由SOI和体Si区域FET的组合构建的SRAM单元的功率和性能。

    Slab inductor device providing efficient on-chip supply voltage conversion and regulation
    34.
    发明授权
    Slab inductor device providing efficient on-chip supply voltage conversion and regulation 有权
    板式电感器件提供有效的片上电源电压转换和调节

    公开(公告)号：US09118242B2

    公开(公告)日：2015-08-25

    申请号：US13595016

    申请日：2012-08-27

    申请人： Leland Chang ,  David Goren ,  Naigang Wang

    发明人： Leland Chang ,  David Goren ,  Naigang Wang

    IPC分类号： G06F1/26 ,  H02M3/155 ,  H02M3/156

    CPC分类号： H02M3/158 ,  G06F1/26 ,  H02M3/155 ,  H02M3/156

    摘要： A method is disclosed to operate a voltage conversion circuit such as a buck regulator circuit that has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches; and a means to reduce or cancel the detrimental effect of other wires on same chip, such as a power grid, potentially conducting return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor.

    摘要翻译： 公开了一种用于操作诸如降压调节器电路的电压转换电路的方法，该电压转换电路具有耦合到电压源的多个开关; 具有长度，宽度和厚度的平板电感器，其中所述平板电感器耦合在所述多个开关之间，并且在所述多个开关的操作期间负载并承载负载电流; 以及减少或消除其他电线对同一芯片（例如电力网）的有害影响的手段，可能导致返回电流，从而降低该板式电感器的功能。 在一个实施例中，电线可以进一步远离板式电感器，并且在另一个实施例中，磁性材料可用于屏蔽平板电感器与至少一个这样的干扰导体。

    Sense scheme for phase change material content addressable memory
    36.
    发明授权
    Sense scheme for phase change material content addressable memory 有权
    相变材料内容可寻址存储器的感应方案

    公开(公告)号：US08687398B2

    公开(公告)日：2014-04-01

    申请号：US13407813

    申请日：2012-02-29

    申请人： Leland Chang ,  Chung H. Lam ,  Jing Li ,  Robert K. Montoye

    发明人： Leland Chang ,  Chung H. Lam ,  Jing Li ,  Robert K. Montoye

    IPC分类号： G11C15/00

    CPC分类号： G11C15/00

    摘要： A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.

    摘要翻译： 一种用于感测内容可寻址存储器中匹配线的感测电路和方法。 感测电路包括电反馈回路中电耦合到匹配线的反相器。 逆变器包括匹配线的反相阈值。 在预充电阶段期间，将匹配线充电至基本上第一电压阈值。 当匹配线电压从基本上从第一电压阈值下降到基本上第二电压阈值时，发生评估阶段。

    Hybrid CMOS technology with nanowire devices and double gated planar devices
    37.
    发明授权
    Hybrid CMOS technology with nanowire devices and double gated planar devices 有权
    具有纳米线器件和双门控平面器件的混合CMOS技术

    公开(公告)号：US08541774B2

    公开(公告)日：2013-09-24

    申请号：US13605076

    申请日：2012-09-06

    申请人： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Leland Chang ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Leland Chang ,  Jeffrey W. Sleight

    IPC分类号： H01L27/06

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/78648 ,  H01L29/78696

    摘要： A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.

    摘要翻译： 衬底包括第一源极区域和第一漏极区域，每个第一漏极区域具有设置在第二半导体层上的第一半导体层和平行于{110}晶面的平面和平行于{110}晶面的相对侧壁表面的表面; 纳米线通道部件由第一源极区域和第一漏极区域悬挂，其中纳米线通道构件包括第一半导体层，以及平行于{100}晶面的相对侧壁表面和平行于{110}晶面的相对面。 衬底还包括具有第一源极和漏极区域的特性的第二源极和漏极区域以及由第二源极区域和第二漏极区域悬置并且具有与纳米线通道构件相同的特性的单个沟道构件。 单通道构件的宽度是单个纳米线构件的宽度的至少几倍。

    Selective floating body SRAM cell
    40.
    发明授权
    Selective floating body SRAM cell 有权
    选择性浮体SRAM单元

    公开(公告)号：US08378429B2

    公开(公告)日：2013-02-19

    申请号：US13045784

    申请日：2011-03-11

    申请人： Josephine B. Chang ,  Leland Chang ,  Steven J. Koester ,  Jeffrey W. Sleight

    发明人： Josephine B. Chang ,  Leland Chang ,  Steven J. Koester ,  Jeffrey W. Sleight

    IPC分类号： H01L21/70

    CPC分类号： H01L27/088 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/7841

    摘要： A memory cell has N≧16 transistors, in which two are access transistors, at least one pair [say (N-2)/2] are pull-up transistors, and at least another pair [say (N-2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.

    摘要翻译： 存储单元具有N≥16个晶体管，其中两个是存取晶体管，至少一对[例如（N-2）/ 2]是上拉晶体管，并且至少另一对[例如（N-2）/ 2 ]是下拉晶体管。 上拉和下拉晶体管都耦合在两个存取晶体管之间。 每个存取晶体管和上拉晶体管是相同类型的，p型或n型。 每个下拉晶体管是另一种类型的p型或n型。 存取晶体管是浮体装置。 下拉晶体管是非浮体器件。 上拉晶体管可以是浮动或非浮动体器件。 还详细描述了制造存储器单元的各种具体实施方式和方法。