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    Antenna-in-package with better antenna performance
    33.
    发明授权
    Antenna-in-package with better antenna performance 有权

    公开(公告)号：US11050135B2

    公开(公告)日：2021-06-29

    申请号：US16884064

    申请日：2020-05-27

    Applicant: MEDIATEK INC.

    Inventor： Yen-Ju Lu ,  Wen-Chou Wu

    IPC: H01L23/34 ,  H01Q1/22 ,  H01Q1/48 ,  H01Q1/52 ,  H01Q21/12 ,  H01Q9/26 ,  H01Q21/06 ,  H01L23/28 ,  H01L23/528 ,  H01L23/64 ,  H01L23/66

    Abstract: An Antenna-in-Package (AiP) includes an interface layer having at least an antenna layer and an insulating layer disposed under the antenna layer. The antenna layer includes a first antenna region and a second antenna region spaced apart from the first antenna region. An integrated circuit die is disposed on the interface layer. The integrated circuit die is interposed between the first antenna region and the second antenna region. The first antenna region includes a first antenna element, a second antenna element extending along a first direction, and a feeding network electrically connecting the first antenna element and the second antenna element to the integrated circuit die. The feeding network, the first antenna element, and the second antenna element are coplanar. A plurality of solder balls is disposed on a surface of the interface layer.

    Semiconductor package with reduced noise
    34.
    发明授权
    Semiconductor package with reduced noise 有权

    公开(公告)号：US10910323B2

    公开(公告)日：2021-02-02

    申请号：US16535019

    申请日：2019-08-07

    Applicant: MEDIATEK INC.

    Inventor： Sheng-Mou Lin ,  Wen-Chou Wu ,  Hsing-Chih Liu

    IPC: H01L23/552 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18

    Abstract: The present disclosure provides a semiconductor package including a bottom package having a substrate, a radio-frequency (RF) die and a system-on-a-chip (SoC) die arranged on the substrate in a side-by-side manner, a molding compound covering the RF die and the SoC die, and an interposer over the molding compound. Connection elements and a column of signal interference shielding elements are disposed on the substrate. The connection elements surround the SoC die. The column of signal interference shielding elements is interposed between the RF die and the SoC die. A top package is mounted on the interposer.

    SEMICONDUCTOR DEVICE WITH AN EM-INTEGRATED DAMPER
    36.
    发明申请
    SEMICONDUCTOR DEVICE WITH AN EM-INTEGRATED DAMPER 审中-公开

    公开(公告)号：US20200051925A1

    公开(公告)日：2020-02-13

    申请号：US16526632

    申请日：2019-07-30

    Applicant: MediaTek Inc.

    Inventor： Yi-Chieh Lin ,  Sheng-Mou Lin ,  Wen-Chou Wu

    IPC: H01L23/552 ,  H01L23/498 ,  H05K1/18 ,  H05K1/11 ,  H05K1/02

    Abstract: A semiconductor device includes a first layer structure, a first layer structure, a second layer structure and a passive electronic component. The second layer structure is disposed below the first layer structure and coupled to a ground. The conductive structure is coupled to the first layer structure. The conductive structure is installed vertically between the first layer structure and the second layer structure, and is coupled to a first pad of the second layer structure. The passive electronic component comprises a first terminal coupled to the first pad of the second layer structure and a second terminal coupled to a second pad of the second layer structure. The conductive structure and the passive electronic component are connected in series between the first layer structure and the ground to form a conductive path for conducting at least one electromagnetic interference signal to the ground.

    ANTENNA-IN-PACKAGE WITH BETTER ANTENNA PERFORMANCE
    37.
    发明申请
    ANTENNA-IN-PACKAGE WITH BETTER ANTENNA PERFORMANCE 审中-公开

    公开(公告)号：US20190131690A1

    公开(公告)日：2019-05-02

    申请号：US16145108

    申请日：2018-09-27

    Applicant: MEDIATEK INC.

    Inventor： Yen-Ju Lu ,  Wen-Chou Wu

    IPC: H01Q1/22 ,  H01L23/64 ,  H01L23/66 ,  H01L23/28 ,  H01L23/528

    Abstract: An Antenna-in-Package (AiP) includes an interface layer, an integrated circuit die disposed on the interface layer, a molding compound disposed on the interface layer and encapsulating the integrated circuit die, and a plurality of solder balls disposed on a bottom surface of the interface layer. The interface layer includes an antenna layer, and an insulating layer between the antenna layer and the ground reflector layer. The antenna layer includes a first antenna region and a second antenna region spaced apart from the first antenna region. The integrated circuit die is interposed between the first antenna region and the second antenna region. The first antenna region is disposed adjacent to a first edge of the integrated circuit die, and the second antenna region is disposed adjacent to a second edge of the integrated circuit die, which is opposite to the first edge.

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