公开(公告)号：US11757796B2

公开(公告)日：2023-09-12

申请号：US17488362

申请日：2021-09-29

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Haggai Eran ,  Liran Liss ,  Yuval Shpigelman ,  Idan Burstein

IPC: H04L61/00 ,  H04L49/00 ,  H04L12/40 ,  H04L49/90

CPC classification number: H04L49/3072 ,  H04L12/40071 ,  H04L49/9042

Abstract: In one embodiment, a system includes a peripheral device including a memory access interface to receive from a host device headers of packets, while corresponding payloads of the packets are stored in a host memory of the host device, and descriptors being indicative of respective locations in the host memory at which the corresponding payloads are stored, a data processing unit memory to store the received headers and the descriptors without the payloads of the packets, and a data processing unit to process the received headers, wherein the peripheral device is configured, upon completion of the processing of the received headers by the data processing unit, to fetch the payloads of the packets over the memory access interface from the respective locations in the host memory responsively to respective ones of the descriptors, and packet processing circuitry to receive the headers and payloads of the packets, and process the packets.

公开(公告)号：US20230214341A1

公开(公告)日：2023-07-06

申请号：US18174668

申请日：2023-02-27

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Tzahi Oved ,  Achiad Shochat ,  Liran Liss ,  Noam Bloch ,  Aviv Heller ,  Idan Burstein ,  Ariel Shahar ,  Peter Paneah

IPC: G06F13/28 ,  G06F3/06

CPC classification number: G06F13/28 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0673 ,  G06F2213/28

Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.

公开(公告)号：US11622028B2

公开(公告)日：2023-04-04

申请号：US17198292

申请日：2021-03-11

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Yuval Shpigelman ,  Idan Burstein ,  Aviv Kfir ,  Liron Mula ,  Niv Aibester ,  Gil Levy

IPC: H04L47/33 ,  H04L69/22 ,  H04L47/12 ,  H04L1/00

Abstract: A network element includes circuitry and multiple ports. The multiple ports are configured to connect to a communication network. The circuitry is configured to receive via one of the ports a packet that originated from a source node and is destined to a destination node, the packet including a mark that is indicative of a cumulative state derived from at least bandwidth utilization conditions of output ports that were traversed by the packet along a path, from the source node up to the network element, to select a port for forwarding the packet toward the destination node, to update the mark of the packet based at least on a value of the mark in the received packet and on a local bandwidth utilization condition of the selected port, and to transmit the packet having the updated mark to the destination node via the selected port.

公开(公告)号：US11558175B2

公开(公告)日：2023-01-17

申请号：US17233591

申请日：2021-04-19

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Miriam Menes ,  Noam Bloch ,  Adi Menachem ,  Idan Burstein ,  Ariel Shahar ,  Maxim Fudim

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/32

Abstract: In one embodiment, data communication apparatus includes a network interface for connection to a network and configured to receive a sequence of data packets from a remote device over the network, the sequence including data blocks, ones of the data blocks having block boundaries that are not aligned with payload boundaries of the packets, and packet processing circuitry to cryptographically process the data blocks using a block cipher so as to write corresponding cryptographically processed data blocks to a memory, while holding segments of respective ones of the received data blocks in the memory, such that the packet processing circuitry stores a first segment of a data block of a first packet in the memory until a second packet is received, and then cryptographically processes the first and second segments together so as to write a corresponding cryptographically processed data block to the memory.

公开(公告)号：US11502948B2

公开(公告)日：2022-11-15

申请号：US17108002

申请日：2020-12-01

Applicant: Mellanox Technologies, Ltd

Inventor： Boris Pismenny ,  Miriam Menes ,  Idan Burstein ,  Liran Liss ,  Noam Bloch ,  Ariel Shahar

IPC: H04L45/00 ,  H04L45/42 ,  G06F11/10 ,  H04L69/163 ,  H04L69/22

Abstract: A system includes a host processor, which has a host memory and is coupled to store data in a non-volatile memory in accordance with a storage protocol. A network interface controller (NIC) receives data packets conveyed over a packet communication network from peer computers containing, in payloads of the data packets, data records that encode data in accordance with the storage protocol for storage in the non-volatile memory. The NIC processes the data records in the data packets that are received in order in each flow from a peer computer and extracts and writes the data to the host memory, and when a data packet arrives out of order, writes the data packet to the host memory without extracting the data and processes the data packets in the flow so as to recover context information for use in processing the data records in subsequent data packets in the flow.

公开(公告)号：US20210400124A1

公开(公告)日：2021-12-23

申请号：US16908776

申请日：2020-06-23

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ilan Pardo ,  Mark B. Rosenbluth ,  Idan Burstein ,  Rui Xu ,  Oded Lempel ,  Tsofia Eshel

IPC: H04L29/06 ,  G06F12/0875 ,  G06F13/40 ,  H04L29/08 ,  H04L12/879

Abstract: In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.

公开(公告)号：US10776272B2

公开(公告)日：2020-09-15

申请号：US15058262

申请日：2016-03-02

Applicant: Mellanox Technologies Ltd.

Inventor： Idan Burstein ,  Diego Crupnicoff ,  Shlomo Raikin ,  Michael Kagan

IPC: G06F12/0831 ,  G06F3/06 ,  G06F12/128 ,  G06F13/28 ,  G06F13/42 ,  G06F15/173 ,  G06F12/0804

Abstract: A memory device includes a target memory, having a memory address space, and a volatile buffer memory, which is coupled to receive data written over a bus to the memory device for storage in specified addresses within the memory address space. A memory controller is configured to receive, via the bus, a flush instruction and, in response to the flush instruction, to immediately flush the data held in the buffer memory with specified addresses within the memory address space to the target memory.

公开(公告)号：US20200084150A1

公开(公告)日：2020-03-12

申请号：US16559640

申请日：2019-09-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Idan Burstein ,  Noam Bloch ,  Roee Moyal ,  Ariel Shahar ,  Yamin Friedman ,  Yuval Shpigelman

IPC: H04L12/801 ,  H04L12/927 ,  H04L12/841 ,  H04L12/863 ,  H04L29/08

Abstract: A network adapter includes circuitry and one or more ports. The ports connect to a communication network including multiple network elements. The circuitry accesses outbound messages that are pending to be sent over the communication network to multiple remote nodes via the ports. At least some of the outbound messages request the remote nodes to send respective amounts of data back to the network adapter. Based on the amounts of data requested by the outbound messages, the circuitry forecasts a bandwidth of inbound response traffic, which is expected to traverse a selected network element in response to the outbound messages toward the network adapter, determines a schedule for transmitting the outbound messages to the remote nodes so that the forecasted bandwidth meets a bandwidth supported by the selected network element, and transmits the outbound messages to the remote nodes in accordance with the determined schedule.

公开(公告)号：US20190140979A1

公开(公告)日：2019-05-09

申请号：US16012826

申请日：2018-06-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan Levi ,  Liran Liss ,  Haggai Eran ,  Noam Bloch ,  Idan Burstein ,  Lior Narkis ,  Avraham Ganor

IPC: H04L12/933 ,  G06F9/455 ,  G06F13/40

Abstract: A network interface controller that is connected to a host and a packet communications network. The network interface controller includes electrical circuitry configured as a packet processing pipeline with a plurality of stages. It is determined in the network interface controller that at least a portion of the stages of the pipeline are acceleration-defined stages. Packets are processed in the pipeline by transmitting data to an accelerator from the acceleration-defined stages, performing respective acceleration tasks on the transmitted data in the accelerator, and returning processed data from the accelerator to receiving stages of the pipeline.

公开(公告)号：US10082858B2

公开(公告)日：2018-09-25

申请号：US14745549

申请日：2015-06-22

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Idan Burstein ,  Shlomo Raikin ,  Noam Bloch

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3209

Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having multiple host resources, information regarding respective power states of the host resources. The data are selectively directed from the peripheral device to the host resources responsively to the respective power states.