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    Efficient delivery of completion notifications
    31.
    发明申请
    Efficient delivery of completion notifications 有权
    有效地交付完成通知

    公开(公告)号：US20140143455A1

    公开(公告)日：2014-05-22

    申请号：US13682773

    申请日：2012-11-21

    Applicant: MELLANOX TECHNOLOGIES LTD.

    Inventor： Ofer Hayut ,  Noam Bloch ,  Michael Kagan ,  Ariel Shachar

    IPC: G06F3/01

    CPC classification number: G06F3/016 ,  G06F13/00 ,  H04L12/00 ,  H04L12/4641

    Abstract: A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to generate completion reports and to write a plurality of the completion reports to the system memory via the bus together in a single bus transaction.

    Abstract translation: 计算机外围设备包括主机接口，其被配置为通过总线与主处理器和主机处理器的系统存储器进行通信。 外围设备中的处理电路被配置为通过在主处理器上运行的客户端进程来接收和执行提交给外围设备的工作项目，并且响应于完成工作项目的执行，生成完成报告并写入多个完成 通过总线在单个总线事务中一起向系统存储器报告。

    Interrupt Handling in a Virtual Machine Environment
    32.
    发明申请
    Interrupt Handling in a Virtual Machine Environment 有权
    虚拟机环境中的中断处理

    公开(公告)号：US20130042242A1

    公开(公告)日：2013-02-14

    申请号：US13652493

    申请日：2012-10-16

    Applicant: Mellanox Technologies Ltd.

    Inventor： Michael Kagan

    IPC: G06F9/455

    CPC classification number: G06F9/45558 ,  G06F9/4812 ,  G06F2009/45579

    Abstract: A method for computing includes running a plurality of virtual machines on a computer having one or more cores and a memory. Upon occurrence of an event pertaining to a given virtual machine during a period in which the given virtual machine is unable to receive an interrupt, an interrupt message is written to a pre-assigned interrupt address in the memory. When the given virtual machine is able to receive the interrupt, after writing of the interrupt message, a context of the given virtual machine is copied from the memory to a given core on which the given virtual machine is running, and a hardware interrupt is automatically raised on the given core responsively to the interrupt message in the memory.

    Abstract translation: 一种用于计算的方法包括在具有一个或多个核心和存储器的计算机上运行多个虚拟机。 在给定虚拟机不能接收到中断的期间发生与给定虚拟机有关的事件时，中断消息被写入存储器中预分配的中断地址。 当给定的虚拟机能够接收中断时，在写入中断消息之后，给定虚拟机的上下文从存储器复制到运行给定虚拟机的给定核心，并且硬件中断是自动的 响应于内存中的中断消息，给定核心上升。

    Hardware-based congestion control for TCP traffic
    36.
    发明授权
    Hardware-based congestion control for TCP traffic 有权

    公开(公告)号：US10237376B2

    公开(公告)日：2019-03-19

    申请号：US15278143

    申请日：2016-09-28

    Applicant: Mellanox Technologies Ltd.

    Inventor： Diego Crupnicoff ,  Michael Kagan ,  Noam Bloch ,  Adi Menachem ,  Idan Burstein

    IPC: H04L12/801 ,  H04L29/06 ,  H04L12/825 ,  H04L12/841

    Abstract: A method for congestion control includes receiving at a destination computer a packet transmitted on a given flow, in accordance with a predefined transport protocol, through a network by a transmitting network interface controller (NIC) of a source computer, and marked by an element in the network with a forward congestion notification. Upon receiving the marked packet in a receiving NIC of the destination computer, a congestion notification packet (CNP) indicating a flow to be throttled is immediately queued for transmission from the receiving NIC through the network to the source computer. Upon receiving the CNP in the transmitting NIC, transmission of further packets on at least the flow indicated by the CNP from the transmitting NIC to the network is immediately throttled, and an indication of the given flow is passed from the transmitting NIC to a protocol processing software stack running on the source computer.

    Regrouping of video data by a network interface controller
    37.
    发明申请
    Regrouping of video data by a network interface controller 审中-公开

    公开(公告)号：US20180367589A1

    公开(公告)日：2018-12-20

    申请号：US15622094

    申请日：2017-06-14

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Dotan Levi ,  Michael Kagan

    IPC: H04L29/06 ,  H04N21/61 ,  H04N21/23

    Abstract: Apparatus for data communications includes a host interface and a network interface, which receives from a packet communication network data packets containing video data comprising interleaved words of luminance data and chrominance data. In one embodiment, packet processing circuitry separates the luminance data from the chrominance data and writes the luminance data, via the host interface, to a luminance buffer in the host memory while writing the chrominance data, via the host interface, to at least one chrominance buffer in the memory, separate from the luminance buffer. In another embodiment, in which the video data include data words of more than eight bits, the packet processing circuitry writes the video data to at least one buffer while justifying the video data in the memory so that the video data with respect to successive pixels in the sequence are byte-aligned in the buffer.

    Network interface controller with direct connection to host memory
    40.
    发明申请
    Network interface controller with direct connection to host memory 有权
    网络接口控制器，与主机内存直接连接

    公开(公告)号：US20160283422A1

    公开(公告)日：2016-09-29

    申请号：US15181436

    申请日：2016-06-14

    Applicant: Mellanox Technologies Ltd.

    Inventor： Diego Crupnicoff ,  Todd Wilde ,  Richard Graham ,  Michael Kagan

    IPC: G06F13/28 ,  G06F13/42 ,  G11C7/10 ,  G06F13/40

    CPC classification number: G06F13/4022 ,  G06F12/0835 ,  G06F13/28 ,  G06F13/36 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/1072

    Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.

    Abstract translation: 用于主计算机的网络接口设备包括网络接口，被配置为向网络发送数据分组和从网络接收数据分组。 分组处理逻辑通过来自主计算机的系统存储器的直接存储器访问（DMA）经由网络接口​​传送和接收的数据分组传送数据。 存储器控制器包括被配置为连接到系统存储器的第一存储器接口和被配置为连接到主计算机的主机复合体的第二存储器接口。 开关逻辑将第一存储器接口交替地耦合到DMA配置中的分组处理逻辑，并以直通配置耦合到第二存储器接口。

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