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    PRIORITIZED POWER BUDGET ARBITRATION FOR MULTIPLE CONCURRENT MEMORY ACCESS OPERATIONS
    31.
    发明申请
    PRIORITIZED POWER BUDGET ARBITRATION FOR MULTIPLE CONCURRENT MEMORY ACCESS OPERATIONS 有权

    公开(公告)号：US20230084630A1

    公开(公告)日：2023-03-16

    申请号：US17668311

    申请日：2022-02-09

    Applicant: Micron Technology, Inc.

    Inventor： Luca Nubile ,  Walter Di Francesco ,  Fumin Gu ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Liang Yu

    IPC: G06F3/06

    Abstract: A memory device includes memory dice, each memory die including: a memory array; a memory to store a data structure; and control logic that includes: multiple processing threads to execute memory access operations on the memory array concurrently; a priority ring counter, the data structure to store an association between a value of the priority ring counter and a subset of the multiple processing threads; a threads manager to increment the value of the priority ring counter before a power management cycle and to identify one or more prioritized processing threads corresponding to the subset of the multiple processing threads; and a peak power manager coupled with the threads manager and to prioritize allocation of power to the one or more prioritized processing threads during the power management cycle.

    INDEPENDENT PLANE ARCHITECTURE IN A MEMORY DEVICE
    32.
    发明申请
    INDEPENDENT PLANE ARCHITECTURE IN A MEMORY DEVICE 有权

    公开(公告)号：US20230059543A1

    公开(公告)日：2023-02-23

    申请号：US17887940

    申请日：2022-08-15

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Giovanni Xotta ,  Dheeraj Srinivasan ,  Ali Mohammadzadeh ,  Karl D. Schuh ,  Guido Luciano Rizzo ,  Jung Sheng Hoei ,  Michele Piccardi ,  Tommaso Vali ,  Umberto Siciliani ,  Rohitkumar Makhija ,  June Lee ,  Aaron S. Yip ,  Daniel J. Hubbard

    IPC: G06F3/06

    Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

    ACCESS LINE MANAGEMENT IN A MEMORY DEVICE
    40.
    发明申请
    ACCESS LINE MANAGEMENT IN A MEMORY DEVICE 有权
    存储设备中的线路管理

    公开(公告)号：US20170076806A1

    公开(公告)日：2017-03-16

    申请号：US15342255

    申请日：2016-11-03

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Benjamin Louie ,  Ali Mohammadzadeh ,  Aaron S. Yip

    IPC: G11C16/24 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26

    CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

    Abstract: Memory devices are configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.

    Abstract translation: 存储器设备被配置为存储在对存储器设备中的特定行存储器单元执行的存储器件操作期间要应用的许多访问线偏置模式。 存储器设备被进一步配置为支持所存储的偏置图案的修改，通过对存储在存储器件中的偏置图案的改变来偏置访问线路提供灵活性。 方法和设备进一步便于在多个偏置条件下执行存储器件操作，以通过调整存储的偏压图案来评估和表征存储器件，而不需要对存储器件的相关联的硬件改变。

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