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    CACHE MANAGEMENT DURING EXECUTION OF A PROGRAM OPERATION
    31.
    发明申请
    CACHE MANAGEMENT DURING EXECUTION OF A PROGRAM OPERATION 有权

    公开(公告)号：US20240378156A1

    公开(公告)日：2024-11-14

    申请号：US18779666

    申请日：2024-07-22

    Applicant: Micron Technology, Inc.

    Inventor： Sushanth Bhushan ,  Dheeraj Srinivasan

    IPC: G06F12/0891

    Abstract: Control logic in a memory device executes a first programming operation to program the set of memory cells to a set of programming levels. A first cache ready signal is generated, the first cache ready signal indicating to a host system to send first data associated with a second programming operation to an input/output (I/O) data cache of the memory device. A second cache ready signal is generated, the second cache ready signal indicating to the host system to send second data associated with the next programming operation to the I/O data cache. The first data associated with the second programming operation is caused to be stored in a cache storage of the memory device.

    Efficient cache program operation with data encoding
    32.
    发明授权
    Efficient cache program operation with data encoding 有权

    公开(公告)号：US12079134B2

    公开(公告)日：2024-09-03

    申请号：US18178105

    申请日：2023-03-03

    Applicant: Micron Technology, Inc.

    Inventor： Sushanth Bhushan ,  Dheeraj Srinivasan

    IPC: G06F12/08 ,  G06F12/0891

    CPC classification number: G06F12/0891

    Abstract: Control logic in a memory device executes a first programming operation to program the set of memory cells to a set of programming levels. A first cache ready signal is generated, the first cache ready signal indicating to a host system to send first data associated with a second programming operation to an input/output (I/O) data cache of the memory device. A first encoded data value and a second encoded data value associated with each memory cell of the set of memory cells are generated. A second cache ready signal is generated, the second cache ready signal indicating to the host system to send second data associated with the next programming operation to the I/O data cache. The first data associated with the second programming operation is caused to be stored in a third data cache of the cache storage. A third cache ready signal is generated, the third cache ready signal indicating to the host system to send third data associated with the second programming operation to the I/O data cache.

    STATUS POLLING BASED ON DIE-GENERATED PULSED SIGNAL
    33.
    发明公开
    STATUS POLLING BASED ON DIE-GENERATED PULSED SIGNAL 审中-公开

    公开(公告)号：US20240231675A1

    公开(公告)日：2024-07-11

    申请号：US18611094

    申请日：2024-03-20

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Dheeraj Srinivasan

    IPC: G06F3/06

    CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0673

    Abstract: A memory system includes a ready busy pin coupled with a plurality of dice and a processing device coupled with the ready busy pin. The processing device is to perform controller operations including waiting to perform any status checks until after assertion of a pulse on a status indicator signal received from the ready busy pin; detecting the pulse being asserted is an extended pulse comprising at least a partial overlap of a first pulse asserted by a first die and a second pulse asserted by a second die of the plurality of dice; initiating a polling delay period in response to detecting assertion of the extended pulse, wherein the polling delay period is greater than a pulse width of the first pulse; and initiating a first status check of dice operations being performed by the plurality of dice in response to detecting expiration of the polling delay period.

    APPARATUS AND METHODS FOR PERFORMING SUCCESSIVE ARRAY OPERATIONS IN A MEMORY
    35.
    发明公开
    APPARATUS AND METHODS FOR PERFORMING SUCCESSIVE ARRAY OPERATIONS IN A MEMORY 审中-公开

    公开(公告)号：US20230298680A1

    公开(公告)日：2023-09-21

    申请号：US18110489

    申请日：2023-02-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Umberto Siciliani ,  Violante Moschiano ,  Walter Di Francesco ,  Dheeraj Srinivasan

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/20

    CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/20

    Abstract: Memories might include a controller configured to cause the memory to prepare a first plurality of memory cells of a block of memory cells for programming from an initialization state of the block of memory cells, program the first data to the first plurality of memory cells, and, in response to receiving a write command associated with a second address corresponding to the block of memory cells and with second data before successfully verifying programming of the first data to the first plurality of memory cells, prepare a second plurality of memory cells of the block of memory cells corresponding to the second address for programming without returning the block of memory cells to the initialization state after programming the first data to the first plurality of memory cells.

    Checking status of multiple memory dies in a memory sub-system
    36.
    发明授权
    Checking status of multiple memory dies in a memory sub-system 有权

    公开(公告)号：US11662939B2

    公开(公告)日：2023-05-30

    申请号：US16946869

    申请日：2020-07-09

    Applicant: Micron Technology, Inc.

    Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh

    IPC: G06F3/06 ,  G06F13/16

    CPC classification number: G06F3/0653 ,  G06F3/0608 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1668

    Abstract: A processing device in a memory sub-system determines whether to check a status of one or more memory dies of the memory device and sends a multi-unit status command to the memory device, the multi-unit status command specifying a plurality of memory units associated with the one or more memory dies of the memory device. The processing device further receives a response to the multi-unit status command, the response comprising a multi-bit value comprising a plurality of bits, wherein each bit of the plurality of bits represents a status of one or more parameters of a plurality of parameters for a corresponding one of the plurality of memory units.

    MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS
    38.
    发明申请
    MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS 有权

    公开(公告)号：US20230039026A1

    公开(公告)日：2023-02-09

    申请号：US17396825

    申请日：2021-08-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

    Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.

    Data programming
    40.
    发明授权
    Data programming 有权

    公开(公告)号：US11334265B2

    公开(公告)日：2022-05-17

    申请号：US16914547

    申请日：2020-06-29

    Applicant: Micron Technology, Inc.

    Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh

    IPC: G06F3/06 ,  G11C11/56 ,  G11C16/10 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0811

    Abstract: Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a controller. The page buffer can be configured to store a number of pages of data in respective caches of the page buffer. The controller can be configured to program the number of pages of data to a first group of cells in the array. The programming operation can include programming the first group of cells to target states encoded with respective data patterns. The programming operation can include incrementally releasing a first of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular first one of the target states.

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