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公开(公告)号：US20200211635A1
公开(公告)日：2020-07-02
申请号：US16812854
申请日：2020-03-09
Applicant: Micron Technology, Inc.
IPC: G11C11/406 , G11C5/14 , G11C11/4091 , G11C8/10 , G11C11/4074
Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for timing refresh operations in a memory device. An apparatus may include an oscillator that provides a periodic signal to one or more refresh timer circuits. Each of the refresh timer circuits is associated with a respective memory bank in the memory device. The refresh timer may include a counter block and a control logic block. The control logic block may gate the periodic signal to the counter block. The counter block may count the row active signal time and the row precharge time. The counter signals may be used by the control logic block to output a number of pumps of a refresh operation.
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32.发明授权公开(公告)号：US10396787B2
公开(公告)日：2019-08-27
申请号：US16034233
申请日：2018-07-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jason M. Johnson
Abstract: Methods and apparatuses are provided for dynamic step size for impedance calibration of a semiconductor device. An example apparatus includes a resistance calibration circuit configured to provide an impedance code to set impedance of a driver circuit. The resistance calibration circuit includes an adder/subtractor circuit configured to change the impedance code by a first step size responsive to the impedance code being less than a value to adjust the impedance of the driver circuit and further configured to change the impedance code by a second step size responsive to the impedance code greater or equal than the value to adjust the impedance of the driver circuit. The second step size is different from the first step size.
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33.发明申请公开(公告)号：US20190238133A1
公开(公告)日：2019-08-01
申请号：US16034233
申请日：2018-07-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jason M. Johnson
CPC classification number: H03K19/0005 , G11C7/1084 , G11C8/10 , G11C11/4093 , G11C2207/2254
Abstract: Methods and apparatuses are provided for dynamic step size for impedance calibration of a semiconductor device. An example apparatus includes a resistance calibration circuit configured to provide an impedance code to set impedance of a driver circuit. The resistance calibration circuit includes an adder/subtractor circuit configured to change the impedance code by a first step size responsive to the impedance code being less than a value to adjust the impedance of the driver circuit and further configured to change the impedance code by a second step size responsive to the impedance code greater or equal than the value to adjust the impedance of the driver circuit. The second step size is different from the first step size.
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公开(公告)号：US20190086469A1
公开(公告)日：2019-03-21
申请号：US15705867
申请日：2017-09-15
Applicant: Micron Technology, Inc.
Inventor： Kevin Gustav Werhane , Jason M. Johnson
IPC: G01R31/28 , H01L25/065 , G01R31/3177
CPC classification number: H01L25/0657 , G01R31/2896 , G01R31/3177 , H01L2225/06544 , H03K19/20
Abstract: Techniques for using a single thru-chip signal path to auto-identify and address each integrated circuit within a stack of integrated circuits upon power-up of stack. In an example, each integrated circuit of the stack can include a single auto-identify input terminal, a single auto-identify output terminal, and control logic configured to receive a logic state on the single auto-identify input terminal, to set an internal indicator to one of three states, and to control a state of the single auto-identify output terminal in response to a power up condition or to a change in the logic state of the single auto-identify input terminal;
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公开(公告)号：US20140157066A1
公开(公告)日：2014-06-05
申请号：US13693899
申请日：2012-12-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jason M. Johnson , Justin Wood , Gregory S. Hendrix , Mark D. Franklin , Daniel F. Eichenberger
IPC: G11C29/10
CPC classification number: G11C29/40
Abstract: Apparatuses and methods for memory testing with data compression is described. An example apparatus includes a plurality of latch test circuits, wherein each of the plurality of latch test circuits is coupled to a corresponding global data line of a memory. Each of the latch test circuits is configured to receive test data and is configured to latch data from the corresponding global data line or a corresponding mask bit. Each of the plurality of latch test circuits is further configured to output data based at least in part on the corresponding mask bit. A comparison circuit is coupled to an output of each of the latch test circuits and is configured to compare output data provided by each of the latch test circuits and provide a comparator output having a logical value indicative of whether all the output data matches.
Abstract translation: 描述了使用数据压缩进行记忆测试的设备和方法。 一个示例性设备包括多个锁存测试电路，其中多个锁存测试电路中的每一个耦合到存储器的对应全局数据线。 每个锁存测试电路被配置为接收测试数据，并且被配置为从相应的全局数据线或相应的屏蔽位锁存数据。 多个锁存测试电路中的每一个进一步被配置为至少部分地基于对应的屏蔽位来输出数据。 比较电路耦合到每个锁存测试电路的输出，并且被配置为比较由每个锁存测试电路提供的输出数据，并提供具有指示所有输出数据是否匹配的逻辑值的比较器输出。
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Patent Agency Ranking
公开(公告)号：US12100476B2
公开(公告)日：2024-09-24
申请号：US17942944
申请日：2022-09-12
Applicant: Micron Technology, Inc.
Inventor： Kari Crane , Kevin G. Werhane , Yoshinori Fujiwara , Jason M. Johnson , Takuya Tamano , Daniel S. Miller
CPC classification number: G11C7/24 , G11C7/1039 , G11C7/1063 , G11C17/16
Abstract: An apparatus includes a TM control circuit that is configured to receive address information corresponding to a TM function and compare the address information with an authorized TM list stored in a memory of the apparatus to determine if there is a match. If there is a match, a latch load signal pulse is output. A TM latch circuit programs one or more latches based on the address information and based on the latch load signal pulse. The TM latch circuit decodes information in the one or more latches and, based on the decoded information, outputs a test mode signal to turn on test mode operations in circuits associated with the TM function. The apparatus includes a plurality of TM functions for testing various features of the apparatus and the authorized TM list identifies which of the plurality of TM functions has been authorized for customer use.
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公开(公告)号：US12100467B2
公开(公告)日：2024-09-24
申请号：US17822032
申请日：2022-08-24
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Takuya Tamano , Jason M. Johnson , Kevin G. Werhane , Daniel S. Miller
CPC classification number: G11C29/789 , G11C29/027 , G11C29/24 , G11C29/4401 , G11C29/46
Abstract: An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.
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公开(公告)号：US20240087625A1
公开(公告)日：2024-03-14
申请号：US17942944
申请日：2022-09-12
Applicant: Micron Technology, Inc.
Inventor： Kari Crane , Kevin G. Werhane , Yoshinori Fujiwara , Jason M. Johnson , Takuya Tamano , Daniel S. Miller
CPC classification number: G11C7/24 , G11C7/1039 , G11C7/1063 , G11C17/16
Abstract: An apparatus includes a TM control circuit that is configured to receive address information corresponding to a TM function and compare the address information with an authorized TM list stored in a memory of the apparatus to determine if there is a match. If there is a match, a latch load signal pulse is output. A TM latch circuit programs one or more latches based on the address information and based on the latch load signal pulse. The TM latch circuit decodes information in the one or more latches and, based on the decoded information, outputs a test mode signal to turn on test mode operations in circuits associated with the TM function. The apparatus includes a plurality of TM functions for testing various features of the apparatus and the authorized TM list identifies which of the plurality of TM functions has been authorized for customer use.
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公开(公告)号：US11670356B2
公开(公告)日：2023-06-06
申请号：US17305878
申请日：2021-07-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yoshinori Fujiwara , Harish V. Gadamsetty , Gary Howe , Dennis G. Montierth , Michael A. Shore , Jason M. Johnson
IPC: G11C11/406 , G11C11/408 , G11C29/44 , G11C29/00 , G11C29/12
CPC classification number: G11C11/40622 , G11C11/4085 , G11C11/4087 , G11C29/4401 , G11C29/787 , G11C2029/1202
Abstract: Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).
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公开(公告)号：US11456049B2
公开(公告)日：2022-09-27
申请号：US16919922
申请日：2020-07-02
Applicant: Micron Technology, Inc.
Inventor： Jason M. Johnson , Dennis G. Montierth
Abstract: Methods of testing memory devices are disclosed. A method may include reading from a number of memory addresses of a memory array of the memory device and identifying each memory address of the number of addresses as either a pass or a fail. The method may further include storing, for each identified fail, data associated with the identified fail in a buffer of the memory device. Further, the method may include conveying, to a tester external to the memory device, at least some of the data associated with each identified fail without conveying address data associated with each identified pass to the tester. Devices and systems are also disclosed.
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