公开(公告)号：US20230044240A1

公开(公告)日：2023-02-09

申请号：US17970459

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Vinh Q. Diep ,  Zhengyi Zhang ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

公开(公告)号：US11488677B2

公开(公告)日：2022-11-01

申请号：US17247435

申请日：2020-12-10

Applicant: Micron Technology, Inc.

Inventor： Kalyan Chakravarthy Kavalipurapu ,  George Matamis ,  Yingda Dong ,  Chang H. Siau

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

公开(公告)号：US20220215890A1

公开(公告)日：2022-07-07

申请号：US17702525

申请日：2022-03-23

Applicant: Micron Technology, Inc.

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/08

Abstract: Control logic in a memory device initiates a program operation on the memory device, and causes a program voltage to be applied to a selected wordline of the memory array during a program phase of the program operation. The control logic further causes a select gate drain coupled with a string of memory cells in the memory array to deactivate during a recovery phase after applying the program voltage, wherein the string of memory cells comprises a plurality of memory cells, and wherein each memory cell of the plurality of memory cells is coupled to a corresponding wordline of a plurality of wordlines in the memory array.

公开(公告)号：US11282582B2

公开(公告)日：2022-03-22

申请号：US16946273

申请日：2020-06-12

Applicant: Micron Technology, Inc.

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10

Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data block of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.

公开(公告)号：US20210166773A1

公开(公告)日：2021-06-03

申请号：US17078161

申请日：2020-10-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Xu ,  Yingda Dong

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A memory might include a common source, a first data line and a second data line, an array of memory cells, a plurality of access lines, and a controller. The array of memory cells might include a first string of memory cells selectively connected between the first data line and the common source and a second string of memory cells selectively connected between the second data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of the first string of memory cells and a control gate of a respective memory cell of the second string of memory cells. The controller may access the array of memory cells. The controller might be configured to implement a source-side seeding operation concurrently with a data line set operation.

公开(公告)号：US20240244845A1

公开(公告)日：2024-07-18

申请号：US18622671

申请日：2024-03-29

Applicant: Micron Technology, Inc.

Inventor： Yifen Liu ,  Yan Song ,  Albert Fayrushin ,  Naiming Liu ,  Yingda Dong ,  George Matamis

IPC: H10B43/27 ,  H01L23/522 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.

公开(公告)号：US11901010B2

公开(公告)日：2024-02-13

申请号：US17247576

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Vinh Q. Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/30 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.

公开(公告)号：US11688474B2

公开(公告)日：2023-06-27

申请号：US17234502

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C7/10 ,  G11C16/04 ,  G11C16/24 ,  G11C7/06 ,  G11C16/30

CPC classification number: G11C16/3459 ,  G11C7/065 ,  G11C7/1048 ,  G11C16/0433 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3409

Abstract: A memory device includes a memory array of memory cells. A page buffer is to apply, to a bit line, a first voltage or a second voltage that is higher than the first voltage during a program verify operation. Control logic operatively coupled with the page buffer is to perform operations including: causing a plurality of memory cells to be programmed with a first program pulse; measuring a threshold voltage for the memory cells; forming a threshold voltage distribution from the measured threshold voltages; classifying, based on the threshold voltage distribution, a first subset of the memory cells as having a faster quick charge loss than that of a second subset of the memory cells; and causing, in response to the classifying, the page buffer to apply the second voltage to the bit line during a program verify operation performed on any of the first subset of memory cells.

公开(公告)号：US20230022858A1

公开(公告)日：2023-01-26

申请号：US17960252

申请日：2022-10-05

Applicant: Micron Technology, Inc.

Inventor： Kalyan Chakravarthy Kavalipurapu ,  George Matamis ,  Yingda Dong ,  Chang H. Siau

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

公开(公告)号：US11508449B2

公开(公告)日：2022-11-22

申请号：US17249433

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Vinh Q. Diep ,  Zhengyi Zhang ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.