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    Method, electronic device and controller for recovering memory array
    31.
    发明授权
    Method, electronic device and controller for recovering memory array 有权
    方法，用于恢复存储器阵列的电子设备和控制器

    公开(公告)号：US09396806B2

    公开(公告)日：2016-07-19

    申请号：US14182314

    申请日：2014-02-18

    Applicant: Macronix International Co., Ltd.

    Inventor： Kuen-Long Chang ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Chao-Hsin Lin

    IPC: G11C29/00 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C16/3418

    Abstract: A method, an electronic device and a controller for recovering an array of memory cells are provided. The method comprises the following steps. Whether a recovery control signal is received or not is determined. A retention checking procedure is executed for identifying whether a threshold voltage distribution of at least one bit of the memory cells in high threshold state is shifted or not, if the recovery control signal is received. A retention writing procedure is executed on the memory cells, if the memory cells in high threshold state do not pass the retention checking procedure.

    Abstract translation: 提供了一种用于恢复存储器单元阵列的方法，电子设备和控制器。 该方法包括以下步骤。 确定是否接收到恢复控制信号。 如果接收到恢复控制信号，则执行保持检查程序，用于识别高阈值状态下的存储器单元的至少一位的阈值电压分布是否移位。 如果高阈值状态的存储单元不通过保留检查程序，则在存储器单元上执行保留写入过程。

    METHOD, ELECTRONIC DEVICE AND CONTROLLER FOR RECOVERING ARRAY OF MEMORY CELLS
    34.
    发明申请
    METHOD, ELECTRONIC DEVICE AND CONTROLLER FOR RECOVERING ARRAY OF MEMORY CELLS 有权
    用于恢复记忆体阵列的方法，电子装置和控制器

    公开(公告)号：US20150143171A1

    公开(公告)日：2015-05-21

    申请号：US14182314

    申请日：2014-02-18

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Chao-Hsin Lin

    IPC: G06F11/14

    CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C16/3418

    Abstract: A method, an electronic device and a controller for recovering an array of memory cells are provided. The method comprises the following steps. Whether a recovery control signal is received or not is determined. A retention checking procedure is executed for identifying whether a threshold voltage distribution of at least one bit of the memory cells in high threshold state is shifted or not, if the recovery control signal is received. A retention writing procedure is executed on the memory cells, if the memory cells in high threshold state do not pass the retention checking procedure.

    Abstract translation: 提供了一种用于恢复存储器单元阵列的方法，电子设备和控制器。 该方法包括以下步骤。 确定是否接收到恢复控制信号。 如果接收到恢复控制信号，则执行保持检查程序，用于识别高阈值状态下的存储器单元的至少一位的阈值电压分布是否移位。 如果高阈值状态的存储单元不通过保留检查程序，则在存储器单元上执行保留写入过程。

    Managing secure writes in semiconductor devices
    36.
    发明授权
    Managing secure writes in semiconductor devices 有权

    公开(公告)号：US12086457B2

    公开(公告)日：2024-09-10

    申请号：US17881078

    申请日：2022-08-04

    Applicant: Macronix International Co., Ltd.

    Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen ,  Chun-Hsiung Hung

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0622 ,  G06F3/0679

    Abstract: Systems, devices, methods, and circuits for managing secure writes in semiconductor devices. In one aspect, a semiconductor device includes a memory array and logic circuitry coupled to the memory array. The logic circuitry is configured to execute a secure write operation in the memory array in response to receiving encrypted information. The encrypted information includes at least one of information of data to be written, an option code, or multiple addresses in the memory array, the option code specifying a way of writing the data on at least one of the multiple addresses in the memory array.

    High performance secure read in secure memory providing a continuous output of encrypted information and specific context
    37.
    发明授权
    High performance secure read in secure memory providing a continuous output of encrypted information and specific context 有权

    公开(公告)号：US11960769B2

    公开(公告)日：2024-04-16

    申请号：US17824226

    申请日：2022-05-25

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chia-Jung Chen ,  Chin-Hung Chang ,  Ken-Hui Chen

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0622 ,  G06F3/0679

    Abstract: A memory device includes a command decoder that implements security logic to detect a command sequence to read a security region of a memory array with continuous encrypted data and to output/input specific contexts for the data. Output/input of specific contexts can be during a dummy cycle to achieve greater performance. A host interfacing can, for example, execute a single command to both get the encrypted data and specific contexts that were used to encrypt the data. Our technology can implement transferring data on the system bus in ciphertext and encrypted by a different Nonce or a different session key than used in a previous transfer operation. In this way, data will be represented with different ciphertext on the bus at different sessions; thereby defending against a replay attack.

    MANAGING SECURE WRITES IN SEMICONDUCTOR DEVICES
    38.
    发明公开
    MANAGING SECURE WRITES IN SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230259301A1

    公开(公告)日：2023-08-17

    申请号：US17881078

    申请日：2022-08-04

    Applicant: Macronix International Co., Ltd.

    Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen ,  Chun-Hsiung Hung

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0622 ,  G06F3/0679

    Abstract: Systems, devices, methods, and circuits for managing secure writes in semiconductor devices. In one aspect, a semiconductor device includes a memory array and logic circuitry coupled to the memory array. The logic circuitry is configured to execute a secure write operation in the memory array in response to receiving encrypted information. The encrypted information includes at least one of information of data to be written, an option code, or multiple addresses in the memory array, the option code specifying a way of writing the data on at least one of the multiple addresses in the memory array.

    Memory chip having security verification function and memory device
    39.
    发明授权
    Memory chip having security verification function and memory device 有权

    公开(公告)号：US11520933B2

    公开(公告)日：2022-12-06

    申请号：US16726284

    申请日：2019-12-24

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Chia-Jung Chen ,  Chin-Hung Chang ,  Ken-Hui Chen

    IPC: G06F21/72 ,  G06F21/62 ,  G06F12/1009

    Abstract: A memory chip comprises a first memory controller, a first data storage zone, a security unit and an address configuration unit. The first data storage zone is coupled to the first memory controller, and represented by a first physical address range. The security unit is coupled to the first memory controller. The address configuration unit is coupled to the first memory controller. The memory chip is configured to be coupled between a host controller and another memory chip. The another memory chip comprises a second data storage zone represented by a second physical address range. The address configuration unit records one or more relationships of a logical address range corresponding to the first physical address range and the second physical address range. The security unit is configured to encrypt and decrypt data in the first data storage zone and the second data storage zone.

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