中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

90 records (took 0.028 seconds)

    Configurable security memory region
    32.
    发明授权
    Configurable security memory region 有权

    公开(公告)号：US10809925B2

    公开(公告)日：2020-10-20

    申请号：US16259268

    申请日：2019-01-28

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Ken-Hui Chen ,  Kuen-Long Chang ,  Chin-Hung Chang ,  Yu-Chen Wang

    IPC: G06F3/06 ,  G06F12/14

    Abstract: A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.

    Memory and method for operating a memory with interruptible command sequence
    33.
    发明授权
    Memory and method for operating a memory with interruptible command sequence 有权

    公开(公告)号：US10289596B2

    公开(公告)日：2019-05-14

    申请号：US15411731

    申请日：2017-01-20

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Ken-Hui Chen ,  Kuen-Long Chang ,  Su-Chueh Lo ,  Chun-Yu Liao

    IPC: G06F13/42 ,  G06F13/16

    Abstract: A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence. Also, the command logic is configured to be responsive to a third command sequence after the second command sequence and its associated embedded operation have been completed, which completes the interrupted first command sequence and enables execution of an embedded operation identified by the first command sequence. A memory controller supporting such protocols is described.

    NESTED WRAP-AROUND MEMORY ACCESS
    35.
    发明申请
    NESTED WRAP-AROUND MEMORY ACCESS 审中-公开

    公开(公告)号：US20170308463A1

    公开(公告)日：2017-10-26

    申请号：US15139252

    申请日：2016-04-26

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

    IPC: G06F12/06

    CPC classification number: G06F12/0623 ,  G06F12/0246 ,  G06F2212/1044 ,  G06F2212/2022 ,  G11C16/08

    Abstract: A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address, initially set to a supplied start address, is offset from a lower boundary of a wrap-around section. Access starts at a wrap starting address and proceeds in a wrap-around manner within a wrap-around section. After access of the address immediately preceding the wrap starting address, the wrap starting address is incremented by the wrap-around section length, or, if the wrap-around section is the last one in the wrap-around block, the wrap starting address is set to the lower boundary of the wrap-around block plus the offset. Access continues until a termination event.

    Method and apparatus for reducing erase time of memory by using partial pre-programming
    36.
    发明授权
    Method and apparatus for reducing erase time of memory by using partial pre-programming 有权
    通过使用部分预编程来减少存储器的擦除时间的方法和装置

    公开(公告)号：US09502121B2

    公开(公告)日：2016-11-22

    申请号：US14518645

    申请日：2014-10-20

    Applicant: Macronix International Co., Ltd.

    Inventor： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC: G11C16/14 ,  G11C16/16 ,  G11C16/34

    CPC classification number: G11C16/14 ,  G11C16/16 ,  G11C16/344

    Abstract: Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.

    Abstract translation: 非易失性存储器阵列的存储单元的特征在于包括至少一个擦除的阈值电压范围和编程的阈值电压范围的多个阈值电压范围之一。 响应于擦除非易失性存储器阵列的一组存储单元的擦除命令，执行至少包括预编程相位和擦除阶段的多个相位。 预编程相位对组内的阈值电压中的第一组存储器单元进行编程，并且不对组中擦除的阈值电压范围内的阈值电压的组中的第二组存储器单元进行编程 。 通过不对第二组存储器单元进行编程，如果第二组存储器单元与第一组存储器单元一起被编程，那么执行预编程相位更快。

    Circuit with output switch
    38.
    发明授权
    Circuit with output switch 有权
    电路带输出开关

    公开(公告)号：US09450577B1

    公开(公告)日：2016-09-20

    申请号：US14742160

    申请日：2015-06-17

    Applicant: Macronix International Co., Ltd.

    Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Su-Chueh Lo ,  Tzu-Ting Chiu

    IPC: H03K3/00 ,  H03K17/16

    CPC classification number: H03K19/018507

    Abstract: An output circuit includes: an output switch including a gate terminal, a drain terminal coupled to an external I/O bus, and a well terminal; a well control circuit, having a well terminal coupled to the well terminal of the output switch, to maintain a well voltage of the output switch at a level not less than a greater of a first voltage and a second voltage; and a gate control circuit coupled to the gate terminal and a the drain terminal of the output switch and to the external I/O bus, and operable to turn off the output switch, to prevent current flow through the output switch from the external I/O bus when an operating voltage of the output circuit is not applied to the output switch, and a bus voltage from an external device is present on the external I/O bus.

    Abstract translation: 输出电路包括：输出开关，包括栅极端子，耦合到外部I / O总线的漏极端子和阱端子; 阱控制电路，具有耦合到输出开关的阱端子的阱端子，以将输出开关的阱电压保持在不小于第一电压和第二电压的较大值的水平; 以及栅极控制电路，其耦合到输出开关的栅极端子和漏极端子和外部I / O总线，并且可操作以关闭输出开关，以防止电流从外部I / O总线流过输出开关， O总线时，输出电路的工作电压不被施加到输出开关，并且来自外部设备的总线电压存在于外部I / O总线上。

    Stabilization of output timing delay
    39.
    发明授权
    Stabilization of output timing delay 有权
    稳定输出定时延时

    公开(公告)号：US09444462B2

    公开(公告)日：2016-09-13

    申请号：US14458936

    申请日：2014-08-13

    Applicant: Macronix International Co., Ltd.

    Inventor： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

    IPC: H03K3/00 ,  H03K19/0185 ,  H03K19/003

    CPC classification number: H03K19/018521 ,  H03K19/00384

    Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. Alternatively, the output buffer delay is variable. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and can include a first delay circuit that generates the first timing signal with a first delay, and a second delay circuit that generates the second timing signal with a second delay that correlates with the output buffer delay.

    Abstract translation: 集成电路包括输出缓冲器和控制电路。 输出缓冲器具有信号输入，信号输出和一组控制输入。 输出缓冲器具有输出缓冲器延迟，并且响应于施加到该组控制输入的控制信号而可调整驱动强度。 或者，输出缓冲器延迟是可变的。 控制电路连接到输出缓冲器的一组控制输入。 控制电路使用第一和第二定时信号来产生控制信号，并且可以包括产生具有第一延迟的第一定时信号的第一延迟电路和产生具有第二延迟的第二定时信号的第二延迟电路， 与输出缓冲区延迟。

    Input pin control
    40.
    发明授权
    Input pin control 有权
    输入引脚控制

    公开(公告)号：US09417640B2

    公开(公告)日：2016-08-16

    申请号：US14274237

    申请日：2014-05-09

    Applicant: Macronix International Co., Ltd.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang ,  Chao-Hsin Lin

    IPC: H03K17/22 ,  G05F1/46

    CPC classification number: G05F1/46 ,  G05F1/468 ,  H03K17/22

    Abstract: An integrated circuit device includes a pad adapted to receive a signal from an external driver. A state register is programmed with a state that indicates a voltage level to set for the pad during initialization of circuitry on the integrated circuit device responsive to the state for the pad. The voltage level may correspond to a logic low level or a logic high level. A voltage holding circuit is coupled to the pad and the state register, and is configured to force the pad to the voltage level in response to an event that causes the initialization.

    Abstract translation: 集成电路器件包括适于从外部驱动器接收信号的焊盘。 状态寄存器被编程为响应于该焊盘的状态而指示在集成电路器件的电路初始化期间为焊盘设置的电压电平的状态。 电压电平可以对应于逻辑低电平或逻辑高电平。 电压保持电路耦合到焊盘和状态寄存器，并且被配置为响应于引起初始化的事件而迫使焊盘达到电压电平。

Patent Agency Ranking