公开(公告)号：US20050253272A1

公开(公告)日：2005-11-17

申请号：US10509898

申请日：2003-03-31

申请人： Hiroto Ohtake ,  Munehiro Tada ,  Yoshimichi Harada ,  Ken'ichiro Hijioka ,  Shinobu Saitoh ,  Yoshihiro Hayashi

发明人： Hiroto Ohtake ,  Munehiro Tada ,  Yoshimichi Harada ,  Ken'ichiro Hijioka ,  Shinobu Saitoh ,  Yoshihiro Hayashi

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813

摘要： A technique is provided for protecting an interlayer insulating film formed of an organic low dielectric constant material from any damage applied in a semiconductor process, and for attaining the decrease leak current in the interlayer insulating film, resulting in the improvement of reliability of a semiconductor device. The semiconductor device according to the present invention has an organic insulating films (5, 26, 28) having openings. The organic insulating films (5, 26, 28) have modified portions (5a, 26a, 28a) facing the openings. The modified portions (5a, 26a, 28a) contains fluorine atoms and nitrogen atoms. The concentration of the fluorine atoms in the modified portions (5a, 26a, 28a) is lower than the concentration of the nitrogen atoms. The above-mentioned modified layers (5a, 26a, 28a) protect the semiconductor device from the damage applied in the semiconductor process, while suppressing the corrosion of the conductors embedded in the openings.

摘要翻译： 提供了一种用于保护由有机低介电常数材料形成的层间绝缘膜的技术，用于在半导体工艺中施加的任何损坏，并且为了获得在层间绝缘膜中的减小的漏电流，从而提高半导体器件的可靠性 。 根据本发明的半导体器件具有具有开口的有机绝缘膜（5,26,28）。 有机绝缘膜（5,26,28）具有面向开口的变形部分（5a，26a，28a）。 改性部分（5a，26a，28a）含有氟原子和氮原子。 改性部分（5a，26a，28a）中氟原子的浓度低于氮原子的浓度。 上述改性层（5a，26a，28a）保护半导体器件免受在半导体工艺中的损坏，同时抑制嵌入在开口中的导体的腐蚀。

公开(公告)号：US08278763B2

公开(公告)日：2012-10-02

申请号：US13238796

申请日：2011-09-21

申请人： Munehiro Tada ,  Hiroto Ohtake ,  Fuminori Ito ,  Yoshihiro Hayashi ,  Hironori Yamamoto

发明人： Munehiro Tada ,  Hiroto Ohtake ,  Fuminori Ito ,  Yoshihiro Hayashi ,  Hironori Yamamoto

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/53295 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a first insulating film is an insulating film formed of at least one layer which contains a siloxane structure containing silicon, oxygen and carbon; the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms; and a modified layer which containing a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film is formed on at least one of an interface between the first insulating film and the metal and an interface between the first insulating film and a second insulating film.

摘要翻译： 本发明提供了一种多层布线技术，其中在布线之间保持有效的低电容的同时获得了布线之间的高粘合性和高绝缘可靠性。 半导体器件的特征在于，第一绝缘膜是由至少一层包含含有硅，氧和碳的硅氧烷结构的层形成的绝缘膜; 第一绝缘膜的内部的硅氧烷结构含有比硅原子数多的碳原子数; 并且在第一绝缘膜和金属之间的界面中的至少一个上形成有含有比第一绝缘膜的内部少的碳原子数和更多数量的单位体积的氧原子的改性层， 第一绝缘膜和第二绝缘膜之间的界面。

公开(公告)号：US08084294B2

公开(公告)日：2011-12-27

申请号：US11884713

申请日：2006-02-14

申请人： Munehiro Tada ,  Tsuneo Takeuchi ,  Yoshihiro Hayashi

发明人： Munehiro Tada ,  Tsuneo Takeuchi ,  Yoshihiro Hayashi

IPC分类号： H01L51/40

CPC分类号： H01L21/3121 ,  B05D1/62 ,  C09D4/00 ,  C23C16/325 ,  C23C16/401 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3148 ,  H01L21/76801 ,  C08G77/04

摘要： An organic silicon film is formed by carrying out chemical vapor deposition with organic silicon compound being used as a raw material gas. The organic silicon compound contains at least silicon, hydrogen and carbon as a constituent thereof, and contains two or more groups having unsaturated bond, per a molecule thereof. The organic silicon compound is used in mixture with a silicon hydride gas.

摘要翻译： 通过用有机硅化合物作为原料气体进行化学气相沉积形成有机硅膜。 有机硅化合物至少含有硅，氢和碳作为其成分，并且每分子含有两个以上具有不饱和键的基团。 有机硅化合物与氢化硅气体混合使用。

公开(公告)号：US20060131754A1

公开(公告)日：2006-06-22

申请号：US11317399

申请日：2005-12-23

申请人： Hiroto Ohtake ,  Masayoshi Tagami ,  Munehiro Tada ,  Yoshihiro Hayashi

发明人： Hiroto Ohtake ,  Masayoshi Tagami ,  Munehiro Tada ,  Yoshihiro Hayashi

IPC分类号： H01L23/48

CPC分类号： H01L21/76813 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3143 ,  H01L21/31633 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A semiconductor device includes a first interconnection layer and a interlayer insulating layer. The first interconnection layer is formed on a upper side of a substrate, and includes a first interconnection. The interlayer insulating layer is formed on the first interconnection layer, and includes a via connected with the first interconnection at one end of the via and a second interconnection connected with the via at another end of the via. The interlayer insulating layer has a relative dielectric constant lower than that of a silicon oxide film. An upper portion of the interlayer insulating layer includes a silicon-oxide film, a silicon nitride film and a silicon oxide film in order from a lower portion.

摘要翻译： 半导体器件包括第一互连层和层间绝缘层。 第一互连层形成在基板的上侧，并且包括第一互连。 层间绝缘层形成在第一互连层上，并且包括在通孔的一端与第一互连连接的通孔和在通孔的另一端与通孔相连的第二互连。 层间绝缘层的相对介电常数比氧化硅膜低。 层间绝缘层的上部从下部开始依次包括氧化硅膜，氮化硅膜和氧化硅膜。

公开(公告)号：US08937023B2

公开(公告)日：2015-01-20

申请号：US13363638

申请日：2012-02-01

申请人： Fuminori Ito ,  Yoshihiro Hayashi

发明人： Fuminori Ito ,  Yoshihiro Hayashi

IPC分类号： H01L23/48 ,  H01L21/316 ,  C23C16/40 ,  C23C18/12 ,  C23C18/14 ,  H01L21/02

CPC分类号： H01L21/31695 ,  C23C16/401 ,  C23C18/1212 ,  C23C18/122 ,  C23C18/14 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/02362

摘要： A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group.

摘要翻译： 一种方法包括通过引入具有环状硅氧烷作为骨架并具有至少一个与侧链结合的挥发性烃基的环状硅氧烷化合物，将含硅化合物引入等离子体中，在基板上形成绝缘膜， 通过向绝缘膜添加能量将绝缘膜与多孔绝缘膜接合。 与环状硅氧烷化合物，挥发性烃基，环状硅氧烷化合物和挥发性烃基的键相比，含硅化合物的分解能力较少。

公开(公告)号：US08648441B2

公开(公告)日：2014-02-11

申请号：US13106590

申请日：2011-05-12

申请人： Kenichiro Hijioka ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

发明人： Kenichiro Hijioka ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

IPC分类号： H01L21/02

CPC分类号： H01L27/10894 ,  H01L21/76811 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.

摘要翻译： 半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。

公开(公告)号：US08629529B2

公开(公告)日：2014-01-14

申请号：US12519706

申请日：2007-12-25

申请人： Naoya Inoue ,  Ippei Kume ,  Jun Kawahara ,  Yoshihiro Hayashi

发明人： Naoya Inoue ,  Ippei Kume ,  Jun Kawahara ,  Yoshihiro Hayashi

IPC分类号： H01L27/06

CPC分类号： H01L23/5228 ,  H01L23/5223 ,  H01L23/53238 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device is produced by fabricating a capacitor element including a lower electrode, a capacitor insulating film, and an upper electrode, and a thin-film resistor element, in the same step. As the lower electrode of the capacitor element is lined with a lower layer wiring layer (Cu wiring), the lower electrode has extremely low resistance substantially. As such, even if the film thickness of the lower electrode becomes thinner, parasitic resistance does not increased. The resistor element is formed to have the same film thickness as that of the lower electrode of the capacitor element. Since the film thickness of the lower electrode is thin, it works as a resistor having high resistance. In the top layer of the passive element, a passive element cap insulating film is provided, which works as an etching stop layer when etching a contact of the upper electrode of the capacitor element.

摘要翻译： 通过在同一步骤中制造包括下电极，电容器绝缘膜和上电极的电容器元件和薄膜电阻器元件来制造半导体器件。 由于电容器元件的下电极衬有下层布线层（Cu布线），所以下电极具有极低的电阻。 因此，即使下电极的膜厚变薄，寄生电阻也不会增加。 电阻元件形成为具有与电容器元件的下电极相同的膜厚度。 由于下部电极的膜厚薄，所以作为具有高电阻的电阻器。 在无源元件的顶层中，设置无源元件帽绝缘膜，当蚀刻电容器元件的上电极的接触时，其被用作蚀刻停止层。

公开(公告)号：US08624328B2

公开(公告)日：2014-01-07

申请号：US12591089

申请日：2009-11-06

申请人： Jun Kawahara ,  Yoshihiro Hayashi ,  Ippei Kume

发明人： Jun Kawahara ,  Yoshihiro Hayashi ,  Ippei Kume

IPC分类号： H01L27/06

CPC分类号： H01L27/0207 ,  H01L23/522 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device including: a semiconductor substrate; a multi-layered wiring structure which is formed over the semiconductor substrate and in which a plurality of wiring layers, each of which is formed by a wiring and an insulating layer, are laminated; and a capacitive element having a lower electrode, a capacitor insulating layer, and an upper electrode which is embedded in the multi-layered wiring structure, wherein at least two or more of the wiring layers are provided between a lower capacitor wiring connected to the lower electrode and an upper capacitor wiring connected to the upper electrode.

摘要翻译： 提供一种半导体器件，包括：半导体衬底; 形成在半导体衬底上并且其中由布线和绝缘层形成的多个布线层被层叠的多层布线结构; 以及具有嵌入在所述多层布线结构中的下电极，电容绝缘层和上电极的电容元件，其特征在于，所述布线层中的至少两个以上设置在与所述下层电极 电极和连接到上电极的上电容器布线。

公开(公告)号：US08618537B2

公开(公告)日：2013-12-31

申请号：US13067386

申请日：2011-05-27

申请人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L29/10

CPC分类号： H01L29/7869 ,  H01L27/0688 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/45 ,  H01L29/458

摘要： A semiconductor device includes, in a first region over a semiconductor substrate, a first insulating layer, a first wiring, a second insulating layer, a third insulating layer, and a via and a second wiring embedded in the second insulating layer and the third insulating layer through a barrier metal, and includes, in a second region, the first insulating layer, a gate electrode, the second insulating layer, a semiconductor layer located, the third insulating layer, and a first electric conductor and a second electric conductor embedded in the third insulating layer so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view through a barrier metal and coupled to the semiconductor layer through the barrier metal.

摘要翻译： 半导体器件包括在半导体衬底上的第一区域中，第一绝缘层，第一布线，第二绝缘层，第三绝缘层以及嵌入第二绝缘层中的通孔和第二布线，以及第三绝缘层 并且在第二区域中包括第一绝缘层，栅电极，第二绝缘层，位于第三绝缘层和第一导电体中的半导体层，以及嵌入在第二绝缘层中的第二导电体 第三绝缘层，以通过势垒金属在平面图中将栅电极夹在与半导体层重叠的位置，并通过阻挡金属耦合到半导体层。

公开(公告)号：US08435828B2

公开(公告)日：2013-05-07

申请号：US13006034

申请日：2011-01-13

申请人： Hironori Yamamoto ,  Yoshihiro Hayashi ,  Jun Kawahara ,  Tatsuya Usami ,  Koichi Ohto

发明人： Hironori Yamamoto ,  Yoshihiro Hayashi ,  Jun Kawahara ,  Tatsuya Usami ,  Koichi Ohto

IPC分类号： H01L51/40

CPC分类号： H01L21/76832 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76883

摘要： A method of manufacturing a semiconductor device includes forming a first insulating film over an underlying film by plasma polymerization of cyclic siloxane, and forming a second insulating film on the first insulating film by plasma polymerization of the cyclic siloxane continuously, after forming the first insulating film. The deposition rate of the first insulating film is slower than the deposition rate of the second insulating film.

摘要翻译： 一种制造半导体器件的方法包括：通过环状硅氧烷的等离子体聚合在下面的膜上形成第一绝缘膜，并且在形成第一绝缘膜之后，通过环状硅氧烷的等离子体聚合在第一绝缘膜上形成第二绝缘膜 。 第一绝缘膜的沉积速度比第二绝缘膜的沉积速度慢。