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    Providing linear relationship between temperature and digital code
    31.
    发明授权
    Providing linear relationship between temperature and digital code 有权
    提供温度和数字代码之间的线性关系

    公开(公告)号：US08475039B2

    公开(公告)日：2013-07-02

    申请号：US12764532

    申请日：2010-04-21

    Applicant: Chan-Hong Chern ,  Steven Swei

    Inventor： Chan-Hong Chern ,  Steven Swei

    IPC: G01K7/00 ,  H01L35/00

    CPC classification number: G01K7/14 ,  G01K7/01 ,  G01K2219/00

    Abstract: Mechanisms for providing linear relationship between temperatures and digital codes are disclosed. In one method, at a particular temperature, a circuit in the sensor provides a temperature dependent reference voltage, and a compared voltage, to a comparator. The temperature dependent reference voltage depends on temperature in complement to absolute temperature or alternatively depends on temperature in proportion to absolute temperature. The compared voltage is generated corresponding to digital analog converter (DAC) codes as inputs. Another circuit varies the DAC codes until the temperature dependent reference voltage and the compared voltage are equal so that the dependent reference voltage corresponds to a DAC code. The various temperatures experienced by the temperature sensing circuit and the DAC codes are substantially linearly related.

    Abstract translation: 公开了提供温度和数字代码之间的线性关系的机制。 在一种方法中，在特定温度下，传感器中的电路向比较器提供与温度相关的参考电压和比较的电压。 温度依赖参考电压取决于温度与绝对温度的补充，或者取决于与绝对温度成比例的温度。 相应的数字模拟转换器（DAC）代码作为输入产生比较电压。 另一个电路改变DAC代码，直到与温度相关的参考电压和比较的电压相等，从而相关的参考电压对应于DAC代码。 温度感测电路和DAC代码经历的各种温度基本上是线性相关的。

    Integrated circuits for providing clock periods and operating methods thereof
    32.
    发明授权
    Integrated circuits for providing clock periods and operating methods thereof 有权
    用于提供时钟周期的集成电路及其操作方法

    公开(公告)号：US08369172B2

    公开(公告)日：2013-02-05

    申请号：US12844204

    申请日：2010-07-27

    Applicant: Chiang Pu ,  Ming-Chieh Huang ,  Chan-Hong Chern

    Inventor： Chiang Pu ,  Ming-Chieh Huang ,  Chan-Hong Chern

    IPC: G11C7/00

    CPC classification number: G05F1/10 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4065

    Abstract: An integrated circuit includes a capacitor. A switch is electrically coupled with the capacitor in a parallel fashion. A comparator includes a first input node, a second input node, and an output node. The second input node is electrically coupled with a first plate of the capacitor. The output node is electrically coupled with the switch. A transistor is electrically coupled with a second plate of the capacitor. A circuit is electrically coupled with a gate of the transistor. The circuit is configured to provide a bias voltage to the gate of the transistor so as to control a current that is supplied to charge the capacitor.

    Abstract translation: 集成电路包括电容器。 开关以并联方式与电容器电耦合。 比较器包括第一输入节点，第二输入节点和输出节点。 第二输入节点与电容器的第一板电耦合。 输出节点与开关电耦合。 晶体管与电容器的第二板电耦合。 电路与晶体管的栅极电耦合。 电路被配置为向晶体管的栅极提供偏置电压，以便控制供给电容器充电的电流。

    VOL up-shifting level shifters
    33.
    发明授权
    VOL up-shifting level shifters 有权
    VOL上移电平转换器

    公开(公告)号：US08207775B2

    公开(公告)日：2012-06-26

    申请号：US12871343

    申请日：2010-08-30

    Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Yuwen Swei ,  Chih-Chang Lin

    Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Yuwen Swei ,  Chih-Chang Lin

    IPC: H03L5/00

    CPC classification number: H03K19/0941 ,  H03K3/356182 ,  H03K19/018514

    Abstract: A representative level-shifter comprises a dynamically biased current source circuit that receives a first voltage, a first and a second unidirectional current-conducting devices, a first and a second pull-down devices, and a pull-up device. The first and second unidirectional current-conducting devices are coupled to the dynamically biased current source circuit. A voltage output of the level-shifter is located at a first node that is located between the current-constant circuit and the second unidirectional current-conducting device. The first and second pull-down devices are coupled to the first and second unidirectional current-conducting devices, respectively. The pull-up device receives a second voltage and is coupled to the dynamically biased current source circuit and the first unidirectional current-conducting device. The pull-up device is configured to dynamically bias the dynamically biased current source circuit such that a voltage drop of the second unidirectional current-conducting device is output at the voltage output responsive to the pull-up device outputting the second voltage to the dynamically biased current source circuit, the first pull-down device being non-conducting and the second pull-down device being conducting.

    Abstract translation: 代表性的电平转换器包括接收第一电压，第一和第二单向导流器件，第一和第二下拉器件以及上拉器件的动态偏置电流源电路。 第一和第二单向导流器件耦合到动态偏置电流源电路。 电平移位器的电压输出位于位于电流恒定电路和第二单向导流器件之间的第一节点处。 第一和第二下拉装置分别耦合到第一和第二单向导流装置。 上拉装置接收第二电压并耦合到动态偏置电流源电路和第一单向导流装置。 上拉装置被配置为动态地偏置动态偏置的电流源电路，使得第二单向导流装置的电压降在电压输出处被输出，响应于上拉装置将第二电压输出到动态偏置 电流源电路，第一下拉装置不导通，第二下拉装置导通。

    Integrated circuits including a charge pump circuit and operating methods thereof
    34.
    发明授权
    Integrated circuits including a charge pump circuit and operating methods thereof 有权
    包括电荷泵电路的集成电路及其操作方法

    公开(公告)号：US08183913B2

    公开(公告)日：2012-05-22

    申请号：US12706886

    申请日：2010-02-17

    Applicant: Steven Swei ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Chan-Hong Chern ,  Ming-Chieh Huang

    Inventor： Steven Swei ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Chan-Hong Chern ,  Ming-Chieh Huang

    IPC: G05F1/10 ,  G05F3/02

    CPC classification number: G05F1/10 ,  G05F3/02 ,  H03L7/0895 ,  H03L7/0896 ,  H03L7/0898

    Abstract: An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.

    Abstract translation: 集成电路包括第一电流源。 第二电流源经由导线与第一电流源电耦合。 开关电路耦合在第一电流源和第二电流源之间。 第一电路耦合在第一节点和第二节点之间。 第一节点设置在第一电流源和开关电路之间。 第二节点与第一电流源耦合。 第一电路被配置为基本上均衡第一节点和第二节点上的电压。 第二电路耦合在第三节点和第四节点之间。 第三节点设置在第二电流源和开关电路之间。 第四节点被布置成与第二电流源耦合。 第二电路被配置为基本上均衡第三节点和第四节点上的电压。

    Sensing circuit, memory device and data detecting method
    37.
    发明授权
    Sensing circuit, memory device and data detecting method 有权
    感应电路，存储器和数据检测方法

    公开(公告)号：US09437257B2

    公开(公告)日：2016-09-06

    申请号：US13765513

    申请日：2013-02-12

    Applicant: Tien-Chun Yang ,  Yue-Der Chih ,  Chan-Hong Chern ,  Tao Wen Chung

    Inventor： Tien-Chun Yang ,  Yue-Der Chih ,  Chan-Hong Chern ,  Tao Wen Chung

    IPC: G11C11/34 ,  G11C7/00 ,  G11C7/02 ,  G11C7/06 ,  G11C7/14 ,  G11C13/00

    CPC classification number: G11C7/062 ,  G11C7/14 ,  G11C13/004 ,  G11C2207/063

    Abstract: A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage.

    Abstract translation: 感测电路包括感测电阻器，参考电阻器和比较器。 比较器具有耦合到感测电阻器的第一输入端，耦合到参考电阻器的第二输入端和输出端。 第一输入被配置为耦合到与存储器单元相关联的数据位线，以接收由流过感测电阻器的存储单元的单元电流引起的感测输入电压。 第二输入被配置为耦合到与参考单元相关联的参考位线，以接收由参考电池流过参考电阻器的参考电流引起的感测参考电压。 比较器被配置为基于感测输入电压和感测参考电压之间的比较，在输出处产生指示存储在存储器单元中的数据的逻辑状态的输出信号。

    Phase interpolator for clock data recovery circuit with active wave shaping integrators
    38.
    发明授权
    Phase interpolator for clock data recovery circuit with active wave shaping integrators 有权
    具有有源波形整形器的时钟数据恢复电路的相位内插器

    公开(公告)号：US08873689B2

    公开(公告)日：2014-10-28

    申请号：US13564758

    申请日：2012-08-02

    Applicant: Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

    Inventor： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

    IPC: H04L7/00

    CPC classification number: H03K5/135 ,  H03H11/20 ,  H03K2005/00052 ,  H04L7/0029

    Abstract: A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal.

    Abstract translation: 用于CDR电路的相位插值器产生具有在两个输入时钟上的电平转换之间的电平转换的输出时钟。 输入时钟驱动交叉耦合差分放大器，输出可根据输入控制值通过可变电流节流或转向相位变化。 差分放大器产生一个输出信号，该输出信号跨越在引导输入时钟之间的转换开始到延迟输入时钟转换结束之间的时间。 输出时钟是线性的，只要两个输入时钟的转换重叠即可。 每个具有串联电阻和电容反馈路径的放大器的积分器耦合到交叉耦合差分放大器的每个输入，这增强了输入时钟上升时间的重叠，并提高了内插输出信号的线性度。

    Automatic misalignment balancing scheme for multi-patterning technology
    40.
    发明授权
    Automatic misalignment balancing scheme for multi-patterning technology 有权
    多图案化技术的自动对准平衡方案

    公开(公告)号：US08709684B2

    公开(公告)日：2014-04-29

    申请号：US13562436

    申请日：2012-07-31

    Applicant: Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching (Jim) Huang ,  Fu-Lung Hsueh

    Inventor： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching (Jim) Huang ,  Fu-Lung Hsueh

    IPC: G03F1/68

    CPC classification number: G03F7/70466 ,  G03F7/70433 ,  G06F17/5077

    Abstract: Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.

    Abstract translation: 本公开的一些方面提供了一种自动平衡多个图案化层的掩模未对准的方法，以最小化掩模未对准的后果。 在一些实施例中，该方法定义了IC布局内的一个或多个双图案化层的布线网格。 路由网格具有沿着第一方向延伸的多个垂直网格线和沿着第二正交方向延伸的多个水平网格线。 在给定方向（例如，水平和垂直方向）上布线网格的交替线被分配不同的颜色。 然后双重图案化层上的形状沿着布线网格以不同颜色的网格线之间交替的方式布线。 通过以这种方式进行布线，减少了由掩模未对准引起的电容耦合的变化。

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