Apparatus for wafer grinding
    31.
    发明授权
    Apparatus for wafer grinding 有权
    晶圆研磨设备

    公开(公告)号:US09120194B2

    公开(公告)日:2015-09-01

    申请号:US13188028

    申请日:2011-07-21

    IPC分类号: B24B7/22 B24D7/14

    CPC分类号: B24B7/228 B24D7/14

    摘要: A grinding wheel comprises an outer base with a first attached grain pad; and an inner frame with a second attached grain pad; and a spindle axis shared by the outer base and the inner frame, wherein at least one of the outer base and the inner frame can move independently along the shared spindle axis; and wherein the outer base, the inner frame, and the shared spindle axis all have a same center. A grinding system comprises an above said grinding wheel, and a wheel head attached to the shared spindle axis, capable of moving vertically, in addition to a motor driving the grinding wheel to spin; and a chuck table for fixing a wafer on top of the chuck table; wherein the grinding wheel overlaps a portion of the chuck table, each capable of spinning to the opposite direction of another.

    摘要翻译: 砂轮包括具有第一附接谷物垫的外基部; 以及具有第二附着谷物垫的内框架; 以及由所述外基座和所述内框架共享的主轴,其中所述外基座和所述内框架中的至少一个可以沿着所述共享主轴轴线独立地移动; 并且其中所述外基座,所述内框架和所述共享主轴轴线都具有相同的中心。 研磨系统包括上述砂轮和附接到共享主轴轴线的能够垂直移动的砂轮头,除了驱动砂轮旋转的马达之外, 以及用于将晶片固定在卡盘台顶部的卡盘台; 其中所述砂轮与所述卡盘台的一部分重叠,所述卡盘台的每一个能够沿相反方向旋转。

    Methods for minimizing edge peeling in the manufacturing of BSI chips
    33.
    发明授权
    Methods for minimizing edge peeling in the manufacturing of BSI chips 有权
    BSI芯片制造中边缘剥离最小化的方法

    公开(公告)号:US09064770B2

    公开(公告)日:2015-06-23

    申请号:US13551457

    申请日:2012-07-17

    IPC分类号: H01L21/02 H01L27/146

    摘要: A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.

    摘要翻译: 一种方法包括在半导体衬底上形成顶部金属线,其中半导体衬底是具有斜面的晶片的一部分。 当顶部金属线暴露时,在斜面上提供蚀刻剂,其中用蚀刻剂喷射的晶片的区域具有形成具有第一直径的第一环的内部限定线。 进行修整步骤以修剪晶片的边缘部分,其中晶片的剩余部分的边缘具有基本上等于或小于第一直径的第二直径。

    Semiconductor device
    34.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号:US08552529B2

    公开(公告)日:2013-10-08

    申请号:US13488958

    申请日:2012-06-05

    IPC分类号: H01L21/02

    摘要: A semiconductor device is disclosed. The device includes a substrate; a first metal layer overlying the substrate; a dielectric layer overlying the first metal layer; and a second metal layer overlying the dielectric layer, wherein the first metal layer comprises: a first body-centered cubic lattice metal layer; a first underlayer, underlying the first body-centered cubic lattice metal layer, wherein the first underlayer is metal of body-centered cubic lattice and includes titanium (Ti), tungsten (W), molybdenum (Mo) or niobium (Nb); and a first interface of body-centered cubic lattice between the first body-centered cubic lattice metal layer and the first underlayer.

    摘要翻译: 公开了一种半导体器件。 该装置包括基板; 覆盖衬底的第一金属层; 覆盖在第一金属层上的电介质层; 以及覆盖所述电介质层的第二金属层,其中所述第一金属层包括:第一体心立方晶格金属层; 第一底层,位于第一体心立方晶格金属层下面,其中第一底层是体心立方晶格的金属,包括钛(Ti),钨(W),钼(Mo)或铌(Nb); 以及在第一体心立方晶格金属层和第一底层之间的体心立方晶格的第一界面。

    VIA/CONTACT AND DAMASCENE STRUCTURES AND MANUFACTURING METHODS THEREOF
    39.
    发明申请
    VIA/CONTACT AND DAMASCENE STRUCTURES AND MANUFACTURING METHODS THEREOF 有权
    威盛/联系人和丹麦结构及其制造方法

    公开(公告)号:US20080211106A1

    公开(公告)日:2008-09-04

    申请号:US11680981

    申请日:2007-03-01

    IPC分类号: H01L21/4763

    CPC分类号: H01L21/76831 H01L21/7684

    摘要: A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.

    摘要翻译: 形成半导体结构的方法包括在衬底上形成电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分,从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面,而第二非导电阻挡层保留在侧壁上 的开幕。 然后形成种子层和导电层,并且单次抛光操作去除种子层和导电层。