公开(公告)号：US20240178189A1

公开(公告)日：2024-05-30

申请号：US18435822

申请日：2024-02-07

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/14 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L2224/16227 ,  H01L2224/18

Abstract: A semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side RDL structure, and a back-side RDL structure. A bridge TSV interconnect component is embedded in the resin molded core. The bridge TSV interconnect component has a silicon substrate portion, an RDL structure integrally constructed on the silicon substrate portion, and TSVs in the silicon substrate portion. A first semiconductor die and a second semiconductor die are mounted on the front-side RDL structure. The first semiconductor die and the second semiconductor die are coplanar.

公开(公告)号：US10818536B2

公开(公告)日：2020-10-27

申请号：US16776343

申请日：2020-01-29

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Hsu Chiang ,  Neng-Tai Shih

IPC: H01L21/683 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/78

Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

公开(公告)号：US20200168497A1

公开(公告)日：2020-05-28

申请号：US16776343

申请日：2020-01-29

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Hsu Chiang ,  Neng-Tai Shih

IPC: H01L21/683 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48

Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

公开(公告)号：US20190287889A1

公开(公告)日：2019-09-19

申请号：US16433426

申请日：2019-06-06

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L21/48

Abstract: A semiconductor package including at least one semiconductor device, a first redistribution layer, a first molding compound, a second molding compound, conductive vias and a second redistribution layer. The first redistribution layer is disposed beneath the semiconductor device and electrically connected to the semiconductor device. The first molding compound is disposed over the first redistribution layer and surrounds the semiconductor device. The second molding compound surrounds the first redistribution layer and at least a part of the first molding compound. The conductive vias extend through the second molding compound. The second redistribution layer is disposed on a surface of the second molding compound away from the first redistribution layer. The second redistribution layer is electrically connected to the first redistribution layer through the conductive vias.

公开(公告)号：US10381302B2

公开(公告)日：2019-08-13

申请号：US15396817

申请日：2017-01-03

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Shih-Fan Kuan ,  Tieh-Chiang Wu

IPC: H01L21/48 ,  H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L23/522 ,  H01L25/065

Abstract: An interposer includes a first redistribution layer, an organic substrate, a capacitor, a hard mask layer, a conductive pillar, and a second redistribution layer. The organic substrate is on the first redistribution layer. The capacitor is embedded in the organic substrate and includes a first electrode layer, a second electrode layer, and a capacitor dielectric layer between the first electrode layer and the second electrode layer. The first electrode layer electrically connects with the first redistribution layer. The hard mask layer is on the organic substrate. The conductive pillar is embedded in the organic substrate and the hard mask layer and electrically connects with the first redistribution layer. The second redistribution layer is on the hard mask layer and electrically connects with the second electrode layer and the conductive pillar.

公开(公告)号：US10354966B2

公开(公告)日：2019-07-16

申请号：US15966447

申请日：2018-04-30

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/00

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

公开(公告)号：US10056338B2

公开(公告)日：2018-08-21

申请号：US14923449

申请日：2015-10-27

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L21/44 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31

Abstract: Some embodiments of the present disclosure disclose a method for forming semiconductor packages. The method includes disposing a plurality of semiconductor chips over a top side of a wafer, molding the plurality of semiconductor chips with a first molding material, and after molding the semiconductor chips, forming a composite layer over the plurality of semiconductor chips.

公开(公告)号：US20180190531A1

公开(公告)日：2018-07-05

申请号：US15910360

申请日：2018-03-02

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Hsu Chiang ,  Neng-Tai Shih

IPC: H01L21/683 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/498 ,  H01L21/78

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2221/68363 ,  H01L2924/00014

Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

公开(公告)号：US20180053708A1

公开(公告)日：2018-02-22

申请号：US15725723

申请日：2017-10-05

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L21/52

CPC classification number: H01L23/498 ,  H01L21/481 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/17104 ,  H01L2224/1751 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2224/83

Abstract: A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A second RDL structure is disposed on the interconnect component. A plurality of first connecting elements is disposed on the second RDL structure. A polish stop layer covers a surface of the interconnect component. A plurality of second connecting elements is disposed on and in the polish stop layer. At least one semiconductor die is mounted on the second connecting elements.

公开(公告)号：US09786586B1

公开(公告)日：2017-10-10

申请号：US15242594

申请日：2016-08-21

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L23/02 ,  H01L23/28 ,  H01L29/40 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/52 ,  H01L21/78

CPC classification number: H01L23/498 ,  H01L21/481 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/17104 ,  H01L2224/1751 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2224/83

Abstract: A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A second RDL structure is disposed on the interconnect component. A plurality of first connecting elements is disposed on the second RDL structure. A polish stop layer covers a surface of the interconnect component. A plurality of second connecting elements is disposed on and in the polish stop layer. At least one semiconductor die is mounted on the second connecting elements.