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    Memory Arrays And Methods Used In Forming A Memory Array
    32.
    发明申请
    Memory Arrays And Methods Used In Forming A Memory Array 有权

    公开(公告)号：US20210217694A1

    公开(公告)日：2021-07-15

    申请号：US16743329

    申请日：2020-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Harsh Narendrakumar Jain ,  Shuangqiang Luo

    IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/762 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers having channel-material strings therein. Conductive vias are formed through insulating material that is directly above the channel-material strings. Individual of the conductive vias are directly electrically coupled to individual of the channel-material strings. After forming the conductive vias, horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Intervening material is formed in the trenches laterally-between and longitudinally-along the immediately-laterally-adjacent memory-block regions. Additional methods and structures independent of method are disclosed.

    Microelectronic devices including staircase structures, and related memory devices and electronic systems
    33.
    发明授权
    Microelectronic devices including staircase structures, and related memory devices and electronic systems 有权

    公开(公告)号：US10580795B1

    公开(公告)日：2020-03-03

    申请号：US16542116

    申请日：2019-08-15

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11573 ,  H01L23/532

    Abstract: A microelectronic device comprises vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures; a staircase structure within the stack structure and having steps comprising edges of at least some of the tiers; a source tier underlying the stack structure and comprising: a source structure, and first discrete conductive structures horizontally separated from one another and the source structure by at least one dielectric material; conductive contact structures on the steps of the staircase structure; and first conductive pillar structures horizontally alternating with the conductive contact structures and vertically extending through the stack structure to the first discrete conductive structures of the source tier. A memory device, a 3D NAND Flash memory device, and an electronic system are also described.

    METHODS OF FORMING MICROELECTRONIC DEVICES
    35.
    发明公开
    METHODS OF FORMING MICROELECTRONIC DEVICES 审中-公开

    公开(公告)号：US20240215232A1

    公开(公告)日：2024-06-27

    申请号：US18428836

    申请日：2024-01-31

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  John D. Hopkins ,  Lifang Xu ,  Nancy M. Lomeli ,  Indra V. Chary ,  Kar Wui Thong ,  Shicong Wang

    IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L21/768 ,  H10B41/50 ,  H10B43/27 ,  H10B43/50

    CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L21/768 ,  H10B41/50 ,  H10B43/27 ,  H10B43/50

    Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure has blocks separated from one another by first dielectric slot structures. Each of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction and comprising opposing staircase structures each having steps comprising edges of the tiers of the stack structure, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with upper surfaces of the two crest regions. At least one second dielectric slot structure is within horizontal boundaries of the stadium structure in the first horizontal direction and partially vertically extends through and segmenting each of the two bridge regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    37.
    发明公开
    Integrated Assemblies and Methods of Forming Integrated Assemblies 审中-公开

    公开(公告)号：US20240049468A1

    公开(公告)日：2024-02-08

    申请号：US18381791

    申请日：2023-10-19

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  Dong Wang ,  Rui Zhang ,  Da Xing ,  Xiao Li ,  Pei Qiong Cheung ,  Xiao Zeng

    IPC: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

    CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

    Abstract: Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.

    Memory Circuitry And Method Used In Forming Memory Circuitry
    38.
    发明公开
    Memory Circuitry And Method Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240046989A1

    公开(公告)日：2024-02-08

    申请号：US17882053

    申请日：2022-08-05

    Applicant: Micron Technology, Inc.

    Inventor： Jiewei Chen ,  Shuangqiang Luo ,  Lifang Xu

    IPC: G11C16/04 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    CPC classification number: G11C16/0483 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower stack comprising vertically-alternating different-composition lower first tiers and lower second tiers. The lower stack comprises lower channel-material strings extending through the lower first tiers and the lower second tiers. An upper stack is formed directly above the lower stack. The upper stack comprises vertically-alternating different-composition upper first tiers and upper second tiers. The upper stack comprises upper channel-material strings of select-gate transistors. Individual of the upper channel-material strings are directly electrically coupled to individual of the lower channel-material strings. The upper and lower first tiers are conductive at least in a finished-circuitry construction. The upper and lower second tiers are insulative and comprise insulative material. An insulator tier comprising insulator material is directly below a lowest of the upper first tiers and directly above an uppermost of the lower first tiers. The insulator material is of different composition from that of the insulative material of the upper second tiers and of different composition from that of the insulative material of the lower second tiers. Other embodiments, including structure, are disclosed.

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