公开(公告)号：US20210287990A1

公开(公告)日：2021-09-16

申请号：US16820046

申请日：2020-03-16

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Christian George Emor ,  Luca Fumagalli ,  John D. Hopkins ,  Rita J. Klein ,  Christopher W. Petz ,  Everett A. McTeer

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A microelectronic device comprises a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20210287989A1

公开(公告)日：2021-09-16

申请号：US16817267

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A microelectronic device comprises a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure comprises vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulating structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and comprise beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US10923657B2

公开(公告)日：2021-02-16

申请号：US16521046

申请日：2019-07-24

Applicant: Micron Technology, Inc.

Inventor： Tsz W. Chan ,  Durai Vishak Nirmal Ramaswamy ,  Qian Tao ,  Yongjun Jeff Hu ,  Everett A. McTeer

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.

公开(公告)号：US20200152651A1

公开(公告)日：2020-05-14

申请号：US16736089

申请日：2020-01-07

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L27/11556 ,  H01L27/11565 ,  H01L21/285 ,  H01L27/11582

Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.

公开(公告)号：US20190221580A1

公开(公告)日：2019-07-18

申请号：US16363296

申请日：2019-03-25

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Chet E. Carter ,  Collin Howder ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/10 ,  H01L21/768 ,  H01L23/528 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L27/11582 ,  H01L21/28568 ,  H01L21/32134 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L29/1037 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4966 ,  H01L29/4975

Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.

公开(公告)号：US10354989B1

公开(公告)日：2019-07-16

申请号：US15980908

申请日：2018-05-16

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Everett A. McTeer ,  Christopher W. Petz ,  Haoyu Li ,  John Mark Meldrim ,  Yongjun Jeff Hu

IPC: G11C11/34 ,  H01L27/02 ,  H01L23/532 ,  G11C5/06 ,  H01L27/12 ,  H01L21/82

Abstract: An integrated assembly having an insulative mass with a first region adjacent to a second region. The first region has a greater amount of one or more inert interstitial elements incorporated therein than does the second region. Also, an integrated assembly which has vertically-extending channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure includes doped semiconductor material in direct contact with bottom regions of the channel material pillars. An insulative mass is along the bottom regions of the channel material pillars. The insulative mass has an upper region over a lower region. The lower region has a greater amount of one or more inert interstitial elements incorporated therein than does the upper region. Also, methods of forming integrated assemblies.

公开(公告)号：US20170309818A1

公开(公告)日：2017-10-26

申请号：US15642673

申请日：2017-07-06

Applicant: Micron Technology, Inc.

Inventor： Tsz W. Chan ,  D.V. Nirmal Ramaswamy ,  Qian Tao ,  Yongjun Jeff Hu ,  Everett A. McTeer

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/145 ,  H01L27/2427 ,  H01L45/04 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/1608

Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.

公开(公告)号：US09716225B2

公开(公告)日：2017-07-25

申请号：US14476312

申请日：2014-09-03

Applicant: Micron Technology, Inc.

Inventor： Tsz W. Chan ,  D. V. Nirmal Ramaswamy ,  Qian Tao ,  Yongjun Jeff Hu ,  Everett A. McTeer

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/145 ,  H01L27/2427 ,  H01L45/04 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/1608

Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.

公开(公告)号：US11705500B2

公开(公告)日：2023-07-18

申请号：US17180312

申请日：2021-02-19

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L29/49 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H01L29/4966 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US20230154856A1

公开(公告)日：2023-05-18

申请号：US18157962

申请日：2023-01-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Everett A. McTeer ,  Yiping Wang ,  Rajesh Balachandran ,  Rita J. Klein ,  Yongjun J. Hu

IPC: H01L23/538 ,  H01L23/532 ,  H01L21/768 ,  G11C5/06 ,  G11C5/02 ,  H01L27/06

CPC classification number: H01L23/5386 ,  H01L23/5385 ,  H01L23/5384 ,  H01L23/53204 ,  H01L21/76877 ,  G11C5/06 ,  G11C5/025 ,  H01L21/76802 ,  H01L27/0688

Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of 3-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.