公开(公告)号：US06984577B1

公开(公告)日：2006-01-10

申请号：US09665422

申请日：2000-09-20

Applicant: Bin Zhao ,  Maureen R. Brongo

Inventor： Bin Zhao ,  Maureen R. Brongo

IPC: H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76832 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A damascene interconnect that reduces interconnect intra-layer capacitance and/or inter-layer capacitance is provided. The damascene interconnect structure has air gaps between metal lines and/or metal layers. The interconnect structure is fabricated to a via level through a processing step prior to forming contact vias, then one or more air gaps are formed into the damascene structure so that the air gaps are positioned between selected metal lines. A sealing layer is then deposited over the damascene structure to seal the air gaps.

Abstract translation: 提供了减少互连层内电容和/或层间电容的镶嵌互连。 镶嵌互连结构在金属线和/或金属层之间具有气隙。 在形成接触通孔之前，通过处理步骤将互连结构制成通孔级，然后将一个或多个气隙形成到镶嵌结构中，使得气隙位于选定的金属线之间。 然后将密封层沉积在镶嵌结构上以密封气隙。

公开(公告)号：US06900938B2

公开(公告)日：2005-05-31

申请号：US10016812

申请日：2001-11-30

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: G02B6/34 ,  G02B5/30

CPC classification number: G02B6/29302 ,  G02B6/272 ,  G02B6/2766 ,  G02B6/2773 ,  G02B6/29386

Abstract: An apparatus for channel interleaving comprises a spatial birefringent device assembly and a reflector which is configured so as to direct light from the spatial birefringent device assembly back through the spatial birefringent device assembly. The spatial birefringent device assembly comprises at least one spatial birefringent device. Directing light from the spatial birefringent device assembly back through the spatial birefringent device assembly substantially mitigates cross-talk and/or dispersion of the apparatus for channel interleaving in communications.

Abstract translation: 用于信道交织的装置包括空间双折射器件组件和反射器，其被配置为将空间双折射器件组件的光引导回空间双折射器件组件。 空间双折射装置组件包括至少一个空间双折射装置。 通过空间双折射器件组件将来自空间双折射器件组件的光引导回来，基本上减轻了通信中用于信道交织的设备的串扰和/或分散。

公开(公告)号：US06731430B2

公开(公告)日：2004-05-04

申请号：US09876484

申请日：2001-06-07

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: G02B530

CPC classification number: G02B27/288

Abstract: A filter for filtering electromagnetic radiation has two polarization selection elements and a birefringent element assembly disposed intermediate polarization selection elements. The birefringent element assembly is configured so as to optimize contributions of a fundamental and at least one odd harmonic of a transmission vs. wavelength curve in a manner which enhances transmission vs. wavelength curve stopband depth and passband flatness, so as to enhance performance and mitigate cross-talk.

Abstract translation: 用于滤波电磁辐射的滤波器具有两个偏振选择元件和设置在偏振选择元件之间的双折射元件组件。 双折射元件组件被配置为以增强透射与波长曲线阻带深度和通带平坦度的方式优化透射与波长曲线的基波和至少一个奇次谐波的贡献，从而增强性能并减轻 相声。

公开(公告)号：US06445073B1

公开(公告)日：2002-09-03

申请号：US09002326

申请日：1998-01-02

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: H01L2940

CPC classification number: H01L21/7681 ,  H01L21/76807 ,  H01L21/7684 ,  H01L2221/1036

Abstract: A semiconductor process and structure is provided for use in single or dual damascene metallization processes. A thin metal layer which serves as an etch stop and masking layer is deposited upon a first dielectric layer. Then, a second dielectric layer is deposited upon the thin metallization masking layer. The thin metallization masking layer provides an etch stop to form the bottom of the in-laid conductor grooves. In a dual damascene process, the thin metallization masking layer leaves open the via regions. Thus, the conductor grooves above the metallization masking layer and the via regions may be etched in the first and second dielectric in one step. In a single damascene process, the thin metallization etch masking layer may cover the via regions. The etch stop and masking layer can be formed from any conductive or non-conductive materials whose chemical, mechanical, thermal and electrical properties are compatible with the process and circuit performance.

Abstract translation: 提供半导体工艺和结构用于单镶嵌金属化或双镶嵌金属化工艺。 用作蚀刻停止和掩蔽层的薄金属层沉积在第一介电层上。 然后，在薄金属化掩模层上沉积第二介电层。 薄金属化掩模层提供蚀刻停止以形成嵌入式导体槽的底部。 在双镶嵌工艺中，薄的金属化掩模层离开通孔区域。 因此，金属化掩模层和通孔区域之上的导体沟槽可以在一个步骤中在第一和第二电介质中蚀刻。 在单个镶嵌工艺中，薄金属化蚀刻掩模层可以覆盖通孔区域。 蚀刻停止和掩蔽层可以由其化学，机械，热和电特性与工艺和电路性能兼容的任何导电或非导电材料形成。

公开(公告)号：US06309922B1

公开(公告)日：2001-10-30

申请号：US09627505

申请日：2000-07-28

Applicant: Q. Z. Liu ,  Bin Zhao ,  David Howard

Inventor： Q. Z. Liu ,  Bin Zhao ,  David Howard

IPC: H01L218234

CPC classification number: H01L28/10 ,  H01L27/08

Abstract: Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a semiconductor die. Thereafter, the entire dielectric layer in the semiconductor die is subjected to a blanket implantation or sputtering of high permeability material. According to another embodiment, a first area in a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor die includes a patterned conductor which is to be used as an inductor. The patterned conductor is also covered, for example, with photoresist. The second area, excluding the covered patterned conductor is subjected to implantation or sputtering of high permeability material. According to yet another embodiment, a first area of a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor area includes a patterned conductor which is to be used as an inductor. This second area, including the patterned conductor, is subjected to implantation or sputtering of high permeability material. The implantation or sputtering of high permeability materials result in the inductors having much higher inductance values than they would otherwise have.

Abstract translation: 公开了片上电感器的制造方法和相关结构。 根据一个实施例，电感器通过在半导体管芯内的某个介电层内图案化导体而形成。 此后，对半导体管芯中的整个电介质层进行高导磁率材料的覆盖注入或溅射。 根据另一实施例，半导体管芯中的第一区域例如被光致抗蚀剂覆盖。 半导体管芯中的第二区域包括用作电感器的图案化导体。 图案化的导体也例如用光致抗蚀剂覆盖。 不包括覆盖图案导体的第二区域经受高磁导率材料的注入或溅射。 根据另一个实施例，半导体管芯的第一区域例如被光致抗蚀剂覆盖。 半导体区域中的第二区域包括用作电感器的图案化导体。 包括图案化导体的该第二区域经受高磁导率材料的注入或溅射。 高磁导率材料的注入或溅射导致电感器的电感值高于原来的电感值。

公开(公告)号：US06271127B1

公开(公告)日：2001-08-07

申请号：US09329569

申请日：1999-06-10

Applicant: Qizhi Liu ,  David Feiler ,  Bin Zhao ,  Maureen R. Brongo

Inventor： Qizhi Liu ,  David Feiler ,  Bin Zhao ,  Maureen R. Brongo

IPC: H01L214763

CPC classification number: H01L21/76829 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76825 ,  Y10S438/949

Abstract: Method for dual damascene metallization of semiconductor workpieces which uses a process for creating an etch stop in an insulator thereby eliminating the need for deposition of an etch stop layer. Electron beam exposure is used to cure the insulator, or material having a low dielectric constant. Application of the electron beam to the low dielectric constant material converts the topmost layer of the low dielectric constant material to an etch stop layer, while rapid thermal heating cures the remainder of the low dielectric constant material. Creation of an etch stop layer in the low dielectric constant material can also be achieved by curing the low dielectric constant material using ion implantation.

Abstract translation: 用于半导体工件的双镶嵌金属化的方法，其使用在绝缘体中产生蚀刻停止的工艺，从而消除了沉积蚀刻停止层的需要。 使用电子束曝光来固化绝缘体或具有低介电常数的材料。 将电子束应用于低介电常数材料将低介电常数材料的最上层转化为蚀刻停止层，同时快速热加热固化低介电常数材料的其余部分。 在低介电常数材料中形成蚀刻停止层也可以通过使用离子注入固化低介电常数材料来实现。

公开(公告)号：US06245663B1

公开(公告)日：2001-06-12

申请号：US09163967

申请日：1998-09-30

Applicant: Bin Zhao ,  Maureen R. Brongo

Inventor： Bin Zhao ,  Maureen R. Brongo

IPC: H01L214763

CPC classification number: H01L21/76834 ,  H01L21/76807 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and structures are disclosed for advanced interconnects in sub-micron and sub-half-micron integrated circuit devices fabricated using a single damascene process. a dielectric etch-stop layer (e.g., silicon nitride) is deposited subsequent to rather than prior to CMP processing of the previous metallization layer (e.g., the conductive plug). This scheme effectively eliminates the effect of CMP-induced erosion on the etch-stop layer and therefore allows an extremely thin etch stop to be used. Moreover, a high etch-selectivity can be obtained for the trench etch, and all etch-stop material is removed from beneath the interconnect metal, thereby reducing parasitic effects. A patterned dielectric layer is used as a metal cap in place of the standard blanket silicon nitride layer, thus preventing the formation of blisters and bubbles associated with trapped moisture and gasses, and reducing interconnect capacitance.

Abstract translation: 公开了使用单个镶嵌工艺制造的亚微米级和次级半微米集成电路器件中的高级互连的方法和结构。 在先前的金属化层（例如，导电插头）的CMP处理之前而不是之前沉积介电蚀刻停止层（例如，氮化硅）。 该方案有效地消除了CMP腐蚀对蚀刻停止层的影响，因此允许使用极薄的蚀刻停止。 此外，可以获得沟槽蚀刻的高蚀刻选择性，并且从互连金属下方去除所有蚀刻停止材料，从而减少寄生效应。 图案化的介电层用作代替标准覆盖氮化硅层的金属盖，从而防止与被捕获的湿气和气体相关联的起泡和气泡的形成，并减少互连电容。

公开(公告)号：US6037664A

公开(公告)日：2000-03-14

申请号：US52215

申请日：1998-03-31

Applicant: Bin Zhao ,  Prahalad K. Vasudev ,  Ronald S. Horwath ,  Thomas E. Seidel ,  Peter M. Zeitzoff

Inventor： Bin Zhao ,  Prahalad K. Vasudev ,  Ronald S. Horwath ,  Thomas E. Seidel ,  Peter M. Zeitzoff

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC classification number: H01L21/76849 ,  H01L21/7681 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/902

Abstract: A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.epsilon.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which via and trench openings are formed in the low-.epsilon. ILD. The dual damascene technique allows for both the via and trench openings to be filled at the same time.

Abstract translation: 一种使用低介电常数材料作为电介质层或多层制造双镶嵌互连结构的技术。 使用低介电常数（低ε）电介质材料在金属化层之间形成层间介电层（ILD）层，其中在低εILD中形成通孔和沟槽开口。 双镶嵌技术允许通孔和沟槽开口同时被填充。

公开(公告)号：US5891513A

公开(公告)日：1999-04-06

申请号：US587262

申请日：1996-01-16

Applicant: Valery M. Dubin ,  Yosef Shacham-Diamand ,  Chiu H. Ting ,  Bin Zhao ,  Prahalad K. Vasudev

Inventor： Valery M. Dubin ,  Yosef Shacham-Diamand ,  Chiu H. Ting ,  Bin Zhao ,  Prahalad K. Vasudev

IPC: C23C18/16 ,  H01L21/288 ,  H01L21/768 ,  H01L23/532 ,  H05K3/04 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  B05D5/12

CPC classification number: H01L21/76843 ,  C23C18/1603 ,  C23C18/1651 ,  C23C18/1689 ,  C23C18/1831 ,  C23C18/1879 ,  C23C18/54 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76874 ,  H01L21/76877 ,  H01L23/53238 ,  H05K3/388 ,  H05K3/465 ,  H01L2924/0002 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/0733 ,  H05K3/045 ,  H05K3/422 ,  H05K3/4661 ,  Y10S977/892

Abstract: A method of utilizing electroless copper deposition to form interconnects on a semiconductor wafer. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is blanket deposited. Then, a contact displacement technique is used to form a thin activation seed layer of copper on the barrier layer. An electroless deposition technique is then used to auto-catalytically deposit copper on the activated barrier layer. The electroless copper deposition continues until the via/trench is filled. Subsequently, the surface is polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) and the SiN layers.

Abstract translation: 一种利用无电铜沉积在半导体晶片上形成互连的方法。 一旦在电介质层中形成通孔或沟槽，则氮化钛（TiN）或钽（Ta）阻挡层被覆盖沉积。 然后，使用接触位移技术在阻挡层上形成铜的薄的活化种子层。 然后使用无电沉积技术在活化的阻挡层上自动催化沉积铜。 继续进行化学镀铜沉积，直到通孔/沟槽被填充。 随后，通过施加化学机械抛光（CMP）来抛光表面以从表面去除多余的铜和阻挡材料，使得剩余的唯一的铜和阻挡材料在通孔/沟槽开口中。 然后，在暴露的铜上方形成覆盖氮化硅（SiN）层，以形成电介质阻挡层。 铜互连通过TiN（或Ta）和SiN层从相邻材料完全封装。

公开(公告)号：US5830805A

公开(公告)日：1998-11-03

申请号：US751631

申请日：1996-11-18

Applicant: Yosi Shacham-Diamand ,  Valery M. Dubin ,  Chiu H. Ting ,  Bin Zhao ,  Prahalad K. Vasudev

Inventor： Yosi Shacham-Diamand ,  Valery M. Dubin ,  Chiu H. Ting ,  Bin Zhao ,  Prahalad K. Vasudev

IPC: C23C18/16 ,  H01L21/288 ,  H01L21/44

CPC classification number: C23C18/1683 ,  H01L21/288 ,  C23C18/1619 ,  Y10S438/908 ,  Y10S438/913

Abstract: An electroless deposition apparatus and a method of electroless deposition that uses a single process chamber for performing multiple processes by moving through the process chamber a variety of fluids one at a time in a sequential order.

Abstract translation: 一种无电沉积装置和无电沉积方法，其使用单个处理室通过以顺序顺序一次一个地通过处理室移动各种流体来执行多个处理。