公开(公告)号：US10338837B1

公开(公告)日：2019-07-02

申请号：US15946600

申请日：2018-04-05

Applicant: QUALCOMM Incorporated

Inventor： Subrato Kumar De ,  Dexter Tamio Chun ,  Yanru Li ,  Bohuslav Rychlik ,  Richard Alan Stewart

IPC: G06F3/06 ,  G06N20/00

Abstract: This disclosure relates to allocating memory resources of a computing device comprising non-volatile random access memory (NVRAM) and dynamic random access memory (DRAM). An exemplary method is performed for every independently executable component of an application and includes determining attributes of the component. The method also includes associating the component with a memory profile of a plurality of memory profiles based on the attributes, wherein each memory profile of the plurality of memory profiles specifies a number of banks of the NVRAM and a number of banks of the DRAM. The method also includes causing the computing device to generate an assignment of the component to banks of the NVRAM and DRAM based on the memory profile associated with the component so the computing device can execute the component using the banks of the NVRAM and DRAM based on the assignment.

公开(公告)号：US09785371B1

公开(公告)日：2017-10-10

申请号：US15081915

申请日：2016-03-27

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Tamio Chun ,  Alain Artieri

IPC: G06F1/32 ,  G06F3/06 ,  G06F12/0862 ,  G11C11/406

CPC classification number: G06F3/0625 ,  G06F1/3275 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/0685 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/222 ,  G06F2212/602 ,  G11C11/40607 ,  Y02D10/13

Abstract: Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem adjusts access to the DRAM based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.

公开(公告)号：US09778871B1

公开(公告)日：2017-10-03

申请号：US15081914

申请日：2016-03-27

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Tamio Chun ,  Alain Artieri

IPC: G06F1/32 ,  G06F3/06 ,  G06F12/0862 ,  G11C11/406 ,  G11C7/10

CPC classification number: G06F1/3296 ,  G06F1/324 ,  G06F1/3275 ,  G06F12/0862 ,  G06F13/1689 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/222 ,  G06F2212/602 ,  G11C11/40607 ,  G11C2211/4067 ,  Y02D10/14

Abstract: Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem controls a DDR clock frequency based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.

公开(公告)号：US20170278554A1

公开(公告)日：2017-09-28

申请号：US15622772

申请日：2017-06-14

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  David Ian West

IPC: G11C7/10 ,  G11C29/02

CPC classification number: G11C7/1072 ,  G11C29/022 ,  G11C29/028

Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The signal is then returned to the SoC, where it may be examined by a closed-loop engine of the SoC. A result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

公开(公告)号：US09767868B2

公开(公告)日：2017-09-19

申请号：US14589145

申请日：2015-01-05

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  David Ian West

IPC: G11C7/10 ,  G11C29/02

CPC classification number: G11C7/1072 ,  G11C29/022 ,  G11C29/028

Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A training signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The training signal is then returned to the SoC, where it may be examined by a closed-loop training engine of the SoC. A training result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop training engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

公开(公告)号：US20170255394A1

公开(公告)日：2017-09-07

申请号：US15448327

申请日：2017-03-02

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Michael Hawjing Lo

IPC: G06F3/06 ,  G06F13/42 ,  G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F12/06 ,  G06F13/1668 ,  G06F13/1673 ,  G06F13/4234 ,  G11C7/1006 ,  G11C2207/102 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state. By reducing the amount of data that is transferred between a host and a memory element, power consumption is reduced.

公开(公告)号：US09552163B1

公开(公告)日：2017-01-24

申请号：US14791340

申请日：2015-07-03

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Tamio Chun

IPC: G06F12/00 ,  G06F3/06 ,  G11C11/56

CPC classification number: G06F3/0608 ,  G06F3/0661 ,  G06F3/0679 ,  G06F11/1072 ,  G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7204 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642

Abstract: Systems, methods, and computer programs are disclosed for providing compressed data storage using non-power-of-two flash cell mapping. One embodiment of a method comprises receiving one or more compressed logical pages to be stored in a NAND flash memory. Binary data in the one or more logical pages is transformed to a quinary representation. The quinary representation comprises a plurality of quinary bits. A binary representation of each of the plurality of quinary bits is transmitted to the NAND flash memory. The binary representation of each of the plurality of quinary bits is converted to a quinary voltage for a corresponding cell in a physical page in the NAND flash memory.

Abstract translation: 公开了系统，方法和计算机程序，用于使用非二功能闪存单元映射提供压缩数据存储。 一种方法的一个实施例包括接收要存储在NAND闪速存储器中的一个或多个压缩逻辑页面。 一个或多个逻辑页面中的二进制数据被转换为五进制表示。 五进制表示包括多个五进制位。 多个五进制位中的每一个的二进制表示被发送到NAND闪速存储器。 多个Quinary位中的每一个的二进制表示被转换为NAND闪速存储器中的物理页面中的对应单元的二次电压。

公开(公告)号：US09542333B2

公开(公告)日：2017-01-10

申请号：US14560450

申请日：2014-12-04

Applicant: QUALCOMM INCORPORATED

Inventor： Stephen Arthur Molloy ,  Dexter Tamio Chun

IPC: G06F12/02 ,  G06F12/10 ,  G11C7/10

CPC classification number: G06F12/1009 ,  G06F12/1072 ,  G06F15/163 ,  G06F2212/1024 ,  G06F2212/2542 ,  G06F2212/657 ,  G11C7/1072

Abstract: Systems, methods, and computer programs are disclosed for allocating memory in a portable computing device having a non-uniform memory architecture. One embodiment of a method comprises: receiving from a process executing on a first system on chip (SoC) a request for a virtual memory page, the first SoC electrically coupled to a second SoC via an interchip interface, the first SoC electrically coupled to a first local volatile memory device via a first high-performance bus and the second SoC electrically coupled to a second local volatile memory device via a second high-performance bus; determining whether a number of available physical pages on the first and second local volatile memory devices exceeds a minimum threshold for initiating replication of memory data between the first and second local volatile memory devices; and if the minimum threshold is exceeded, allocating a first physical address on the first local volatile memory device and a second physical address on the second local volatile memory device to a single virtual page address.

Abstract translation: 公开了用于在具有非均匀存储器架构的便携式计算设备中分配存储器的系统，方法和计算机程序。 一种方法的一个实施例包括：从在第一片上系统（SoC）上执行对虚拟存储器页的请求的处理，所述第一SoC经由芯片间接口电耦合到第二SoC，所述第一SoC电耦合到 第一本地易失性存储器设备经由第一高性能总线，并且所述第二SoC经由第二高性能总线电耦合到第二本地易失性存储器设备; 确定所述第一和第二本地易失性存储器设备上的多个可用物理页是否超过用于在所述第一和第二本地易失性存储器设备之间启动存储器数据的复制的最小阈值; 并且如果超过所述最小阈值，则将所述第一本地易失性存储器设备上的第一物理地址和所述第二本地易失性存储器设备上的第二物理地址分配到单个虚拟页地址。

公开(公告)号：US09507675B2

公开(公告)日：2016-11-29

申请号：US14253770

申请日：2014-04-15

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Tamio Chun ,  Yanru Li ,  Jung Pill Kim ,  Deepti Vijayalakshmi Sriramagiri

IPC: G06F11/20 ,  G06F11/10 ,  G06F11/14 ,  G06F11/07 ,  G06F11/08 ,  G11C29/00 ,  G11C29/52 ,  G06F3/06 ,  G11C29/08

CPC classification number: G06F11/2017 ,  G06F3/0688 ,  G06F11/0772 ,  G06F11/08 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1417 ,  G06F2201/85 ,  G06F2212/1032 ,  G06F2212/7201 ,  G11C29/00 ,  G11C29/08 ,  G11C29/52 ,  G11C29/70

Abstract: Systems, methods, and computer programs are disclosed for recovering from dynamic random access memory (DRAM) defects. One method comprises determining that an uncorrected bit error has occurred for a physical codeword address associated with a dynamic random access memory (DRAM) device coupled to a system on chip (SoC). A kernel page associated with a DRAM page comprising the physical codeword address is identified as a bad page. Recovery from the uncorrected bit error is provided by rebooting a system comprising the SoC and the DRAM device. In response to the rebooting, the identified kernel page is excluded from being allocated for DRAM operation.

Abstract translation: 公开了用于从动态随机存取存储器（DRAM）缺陷中恢复的系统，方法和计算机程序。 一种方法包括确定与耦合到片上系统（SoC）的动态随机存取存储器（DRAM）设备相关联的物理码字地址已经发生未校正的位错误。 与包括物理码字地址的DRAM页面相关联的内核页面被识别为坏页面。 通过重新启动包括SoC和DRAM设备的系统来提供从未校正的位错误的恢复。 响应于重新启动，识别的内核页面被排除在为DRAM操作分配之前。

公开(公告)号：US09495261B2

公开(公告)日：2016-11-15

申请号：US14458009

申请日：2014-08-12

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Dexter Tamio Chun ,  Deepti Vijayalakshmi Sriramagiri ,  Mosaddiq Saifuddin ,  Xiangyu Dong ,  Sungryul Kim ,  Yanru Li ,  Jungwon Suh

IPC: G06F11/00 ,  G06F11/20 ,  G11C29/52 ,  G06F11/08 ,  G06F11/30 ,  G11C29/44 ,  G11C29/04

CPC classification number: G06F11/2053 ,  G06F11/073 ,  G06F11/0775 ,  G06F11/0793 ,  G06F11/08 ,  G06F11/1048 ,  G06F11/3037 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/0409

Abstract: Methods and systems for an in-system repair process that repairs or attempts to repair random bit failures in a memory device are provided. In some examples, an in-system repair process may select alternative steps depending on whether the failure is correctable or uncorrectable. In these examples, the process uses communications between a system on chip and the memory to fix the failures during normal operation.

Abstract translation: 提供了修复或尝试修复存​​储器件中的随机位故障的系统内修复过程的方法和系统。 在一些示例中，系统内修复过程可以根据故障是可校正还是不可校正来选择替代步骤。 在这些示例中，该过程使用片上系统与存储器之间的通信来在正常操作期间修复故障。