公开(公告)号：US20130235639A1

公开(公告)日：2013-09-12

申请号：US13869086

申请日：2013-04-24

Applicant: QUALCOMM INCORPORATED

Inventor： Kangho Lee ,  Taehyun Kim ,  Xia Li ,  Jung Pill Kim ,  Seung H. Kang

IPC: G11C5/02 ,  G11C5/08

CPC classification number: G11C5/025 ,  G11C5/08 ,  G11C11/165 ,  H01L27/0207 ,  Y10T29/49117

Abstract: A large scale memory array includes a. uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.

Abstract translation: 大型存储器阵列包括a。 均匀大小的虚拟位单元和有源位单元的统一模式。 大规模存储器阵列中的子阵列由虚拟位单元分隔开。 信号分配电路形成为具有对应于虚拟位单元的宽度或高度的宽度或高度，使得信号分配电路占据与虚拟位单元相同的覆盖区，而不会破坏整个大规模阵列上的均匀图案。 类似大小或大于标准尺寸位单元的边缘虚拟单元可以放置在大规模阵列的边缘周围，以进一步减少图案负载影响。

公开(公告)号：US10263645B2

公开(公告)日：2019-04-16

申请号：US15716451

申请日：2017-09-26

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook Jung ,  Sara Choi ,  Byung Kyu Song ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim ,  Seung Hyuk Kang

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/15

Abstract: In an embodiment, an error detection and correction apparatus includes a positive edge triggered flip-flop that receives syndrome input based on a syndrome output a syndrome generator indicating whether or not input data includes an error, whereby the positive edge triggered flip-flop further provides a syndrome output to an error location decoder.

公开(公告)号：US09612908B2

公开(公告)日：2017-04-04

申请号：US14627268

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Sungryul Kim ,  Jung Pill Kim

IPC: G06F11/00 ,  G06F11/14 ,  G06F12/02 ,  G06F11/10

CPC classification number: G06F11/1402 ,  G06F11/106 ,  G06F12/023 ,  G06F12/0238 ,  G06F2201/805 ,  G06F2212/7205 ,  Y02D10/13

Abstract: Aspects of the disclosure involve memory data scrubber circuits configured to perform memory data scrubbing operations in a processor-based memory to provide data error correction in response to periodic memory controller wake-up periods. Memory data scrubbing is performed to correct errors in data words stored in memory. Memory data scrubbing is initiated in the memory to conserve power in response to periodic memory controller wake-up periods during processor idle periods. Further, in certain aspects disclosed herein, the memory data scrubber circuit is provided as a separate system outside of the memory controller in the memory system. In this manner, power consumption can be further reduced, because the memory data scrubber circuit can continue with memory data scrubbing operations in the memory independent of the memory controller operation, and after the memory controller access commands issued during the wake-up period are completed and the memory controller is powered-down.

公开(公告)号：US09583170B2

公开(公告)日：2017-02-28

申请号：US14620487

申请日：2015-02-12

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00

CPC classification number: G11C11/1675 ,  G11C11/1677 ,  G11C2013/0078

Abstract: Aspects of adjusting resistive memory write driver strength based on a mimic resistive memory write operation are disclosed. In one aspect, a write driver adjustment circuit is provided to adjust a write current provided by a write driver to a resistive memory for write operations. The write driver adjustment circuit includes a mimic write driver configured to provide a mimic write current that mimics the write current provided to the resistive memory. The mimic write current is applied to a mimic resistive memory that contains mimic resistive memory elements that mimic a resistance distribution of the resistive memory. When the mimic write current is applied, a mimic voltage is generated across the mimic resistive memory elements. The write driver adjustment circuit is configured to adjust the write current based on the mimic voltage so that the write current is sufficient for write operations, but low enough to reduce breakdown.

Abstract translation: 公开了基于模拟电阻式存储器写入操作来调节电阻性存储器写入驱动器强度的方面。 一方面，提供写入驱动器调整电路以将由写入驱动器提供的写入电流调整到用于写入操作的电阻性存储器。 写驱动器调整电路包括模拟写驱动器，其配置为提供模拟写入电流，模拟写入电流提供给电阻存储器。 模拟写入电流被施加到模拟电阻性存储器，其包含模拟电阻性存储器的电阻分布的模拟电阻存储器元件。 当应用模拟写入电流时，在模拟电阻存储器元件之间产生模拟电压。 写入驱动器调整电路被配置为基于模拟电压来调整写入电流，使得写入电流对于写入操作是足够的，但是足够低以减少击穿。

公开(公告)号：US09455031B2

公开(公告)日：2016-09-27

申请号：US14161850

申请日：2014-01-23

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim

IPC: G11C11/00 ,  G11C13/00 ,  G11C5/06 ,  G11C7/08 ,  G11C29/02

CPC classification number: G11C13/004 ,  G11C5/063 ,  G11C7/08 ,  G11C11/1673 ,  G11C13/0038 ,  G11C13/0069 ,  G11C29/026 ,  G11C29/028 ,  G11C2013/0054

Abstract: A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits.

Abstract translation: 存储器具有多个非易失性电阻（NVR）存储器阵列，每个存储阵列具有通过参考电路耦合到参考线的参考电压产生电路，该参考电压产生电路耦合到用于该NVR存储器阵列的读出放大器。 参考线耦合链路耦合不同NVR存储器阵列的参考线。 可选地，不同的参考耦合链路被去除或打开，在不同的参考线上获得各自不同的平均和隔离参考电压。 可选地，去除或打开不同的参考电路耦合链路，在参考线上获得各自不同的平均电压，以及解耦和隔离不同的参考电路。

公开(公告)号：US20160267959A1

公开(公告)日：2016-09-15

申请号：US14644631

申请日：2015-03-11

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/79 ,  G11C2213/82

Abstract: Aspects disclosed in the detailed description include write driver circuits for resistive random access memory (RAM) arrays. In one aspect, a write driver circuit is provided to facilitate writing data into a resistive RAM array in a memory system. The write driver circuit is coupled to a selector circuit configured to select a memory bitcell(s) in the resistive RAM array for a write operation. An isolation circuit is provided in the write driver circuit to couple a current source to the selector circuit to provide a write voltage during the write operation and to isolate the current source from the selector circuit when the selector circuit is not engaged in the write operation. By isolating the selector circuit from the current source when the selector circuit is on standby, it is possible to reduce leakage current in the selector circuit, thus reducing standby power consumption in the memory system.

Abstract translation: 在详细描述中公开的方面包括用于电阻随机存取存储器（RAM）阵列的写入驱动器电路。 在一个方面，提供写入驱动器电路以便于将数据写入存储器系统中的电阻式RAM阵列。 写驱动器电路耦合到选择器电路，其被配置为选择用于写入操作的电阻RAM阵列中的存储器位单元。 在写入驱动器电路中提供隔离电路，以将电流源耦合到选择器电路以在写入操作期间提供写入电压，并且当选择器电路未被接合在写入操作中时将电流源与选择器电路隔离。 当选择器电路处于待机状态时，通过将选择器电路与电流源隔离，可以减少选择器电路中的漏电流，从而降低存储系统的待机功耗。

公开(公告)号：US09275714B1

公开(公告)日：2016-03-01

申请号：US14499050

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Sungryul Kim ,  Jung Pill Kim ,  Xiangyu Dong

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1693

Abstract: Systems and methods relate to a read operation on a magnetoresistive random access memory (MRAM). Prior to determining whether there is a hit in the MRAM for a first address corresponding to the read operation, a dummy word line is activated, based on at least a subset of bits of the first address. A settling process for a reference voltage for reading MRAM bit cells at the first address is initiated, based on dummy cells connected to the dummy word line and a settled reference voltage is obtained. If there is a hit, a first word line is activated based on a row address determined from the first address, and the MRAM bit cells at the first address are read using the settled reference voltage.

Abstract translation: 系统和方法涉及磁阻随机存取存储器（MRAM）上的读取操作。 在确定MRAM中是否存在与读取操作相对应的第一地址的命中之前，基于第一地址的位的至少一个子集，激活伪字线。 基于与虚拟字线连接的虚拟单元，启动用于读取第一地址的MRAM位单元的参考电压的稳定处理，并获得稳定的参考电压。 如果存在命中，则基于从第一地址确定的行地址来激活第一字线，并且使用稳定的参考电压读取第一地址处的MRAM位单元。

公开(公告)号：US09224467B2

公开(公告)日：2015-12-29

申请号：US14147817

申请日：2014-01-06

Applicant: QUALCOMM Incorporated

Inventor： Wuyang Hao ,  Jungwon Suh ,  Kangho Lee ,  Taehyun Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16

CPC classification number: G11C13/0069 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/72 ,  G11C2213/74

Abstract: A resistance-based memory includes a two-diode access device. In a particular embodiment, a method includes biasing a bit line with a first voltage. The method further includes biasing the sense line with a second voltage. Biasing the bit line and biasing the sense line generates a current through a resistance-based memory element and through one of a first diode and a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.

Abstract translation: 基于电阻的存储器包括二极管接入设备。 在特定实施例中，一种方法包括利用第一电​​压来偏置位线。 该方法还包括利用第二电压来偏置感测线。 偏置位线并偏置感测线通过电阻型存储元件并通过第一二极管和第二二极管之一产生电流。 第一二极管的阴极耦合到位线，并且第二二极管的阳极耦合到感测线。

公开(公告)号：US09093462B2

公开(公告)日：2015-07-28

申请号：US13887723

申请日：2013-05-06

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Brian M. Henderson ,  Shiqun Gu ,  Chiew-Guan Tan ,  Jung Pill Kim ,  Taehyun Kim

IPC: H01L23/48 ,  H01L29/66 ,  H01L23/498 ,  H01L29/861 ,  H01L23/60 ,  H01L25/065 ,  H01L27/02 ,  H01L27/06

CPC classification number: H01L29/66128 ,  H01L21/304 ,  H01L21/762 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/535 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/0694 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/66143 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Abstract translation: 一种方法包括使衬底的背面变薄以暴露形成在衬底中的第一通孔的一部分。 该方法还包括在衬底的背面形成第一二极管。 第一二极管耦合到第一通孔。

公开(公告)号：US08614912B2

公开(公告)日：2013-12-24

申请号：US13869086

申请日：2013-04-24

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Taehyun Kim ,  Xia Li ,  Jung Pill Kim ,  Seung H. Kang

IPC: G11C11/14

CPC classification number: G11C5/025 ,  G11C5/08 ,  G11C11/165 ,  H01L27/0207 ,  Y10T29/49117

Abstract: A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.

Abstract translation: 大规模存储器阵列包括统一大小的虚拟位单元和有源位单元的均匀图案。 大规模存储器阵列中的子阵列由虚拟位单元分隔开。 信号分配电路形成为具有对应于虚拟位单元的宽度或高度的宽度或高度，使得信号分配电路占据与虚拟位单元相同的覆盖区，而不会破坏整个大规模阵列上的均匀图案。 类似大小或大于标准尺寸位单元的边缘虚拟单元可以放置在大规模阵列的边缘周围，以进一步减少图案负载影响。