公开(公告)号：US20200381344A1

公开(公告)日：2020-12-03

申请号：US16424700

申请日：2019-05-29

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Kuiwon KANG ,  Zhijie WANG

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L21/48 ,  H01L23/00

Abstract: Certain aspects of the present disclosure generally relate to a chip package having a split conductive pad for coupling to a device terminal. An example chip package generally includes a layer, a first plurality of conductive pads disposed on the layer, at least one conductive trace disposed on the layer and between the first plurality of conductive pads, and an electrical component having a first terminal coupled to the first plurality of conductive pads and disposed above the at least one conductive trace.

公开(公告)号：US20200350260A1

公开(公告)日：2020-11-05

申请号：US16400264

申请日：2019-05-01

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Kuiwon KANG ,  Zhijie WANG ,  Ming YI

IPC: H01L23/552 ,  H01L23/04 ,  H01L21/52 ,  H01L23/498

Abstract: Certain aspects of the present disclosure provide an integrated circuit (IC) package and techniques for fabricating the IC package. The IC package generally includes a substrate, an IC disposed above the substrate, and a shielding layer coupled to a layer of the substrate, wherein the shielding layer is disposed above the substrate adjacent to the IC, and below an upper surface of the IC.

公开(公告)号：US20240429141A1

公开(公告)日：2024-12-26

申请号：US18340556

申请日：2023-06-23

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Xuefeng ZHANG ,  Aniket PATIL

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

Abstract: A device comprising a package. The package comprises a package substrate; a first integrated device coupled to the package substrate through a first plurality of bump interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of bump interconnects; and a plurality of side wall interconnects coupled to the encapsulation layer and the metallization portion.

公开(公告)号：US20240363514A1

公开(公告)日：2024-10-31

申请号：US18646659

申请日：2024-04-25

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Joan Rey Villarba BUOT

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L24/17 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/81815

Abstract: A package comprising a package substrate and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The package substrate comprises an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, and a second metallization portion coupled to a second surface of the encapsulated portion. The encapsulated portion comprises a first interconnection portion block, a second interconnection portion block, a plurality of pillar interconnects, and an encapsulation layer at least partially encapsulating the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. The plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block and a second plurality of pillar interconnects coupled to the second interconnection portion block.

公开(公告)号：US20240319455A1

公开(公告)日：2024-09-26

申请号：US18607170

申请日：2024-03-15

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Aniket PATIL ,  Dongming HE

IPC: G02B6/42 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: G02B6/4245 ,  G02B6/4248 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16155 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2924/1427 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/182

Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

公开(公告)号：US20240304503A1

公开(公告)日：2024-09-12

申请号：US18179223

申请日：2023-03-06

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Brigham NAVAJA

IPC: H01L21/66 ,  H01L21/48 ,  H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H05K3/40

CPC classification number: H01L22/32 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/0268 ,  H05K1/113 ,  H05K3/4038 ,  H05K2201/0969

Abstract: Disclosed are apparatuses and techniques for fabricating the apparatuses. In an aspect, an apparatus includes an outer connection layer. The outer connection layer has an outer substrate and an outer metallization layer (ML). The outer ML includes a first set of sense split pads. The first set of sense split pads includes a first pad portion and a second pad portion and a test line. The test line is coupled to the first pad portion. The first pad portion and the second pad portion are electrically coupled to a same interconnect.

公开(公告)号：US20240276739A1

公开(公告)日：2024-08-15

申请号：US18168331

申请日：2023-02-13

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Zhijie WANG

IPC: H10B80/00 ,  H01L23/00 ,  H01L23/498 ,  H01L25/16

CPC classification number: H10B80/00 ,  H01L23/49833 ,  H01L24/16 ,  H01L25/162 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2924/1436 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106

Abstract: Disclosed is a stacked substrate package that incorporate surface mounted devices (SMD) between the base and interposer substrates. The SMDs, which may be passive devices (e.g., capacitor, inductor, resistor, etc.), may be electrically coupled to power distribution routing layers of the base and/or the interposer substrates. In this way, clean power may be provided to the devices (e.g., SoC dies, memory dies, etc.) of the stacked substrate package.

公开(公告)号：US20230163113A1

公开(公告)日：2023-05-25

申请号：US17532754

申请日：2021-11-22

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Durodami LISK ,  Hong Bok WE ,  Charles David PAYNTER

IPC: H01L25/10 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/49816 ,  H01L25/50 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227

Abstract: A device comprising a first package and a second package coupled to the first package through a first plurality of solder interconnects. The first package includes a first substrate comprising at least one first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes a second substrate comprising at least one second dielectric layer and a second plurality of interconnects, a second integrated device coupled to a first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate through a second plurality of solder interconnects and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects is located between solder interconnects from the second plurality of solder interconnects.

公开(公告)号：US20230154829A1

公开(公告)日：2023-05-18

申请号：US17455576

申请日：2021-11-18

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Joan Rey Villarba BUOT ,  Aniket PATIL

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L21/76804

Abstract: Disclosed is a stack via structure in which a plurality of vias are stacked over each other. At least one via is a via that has a recess formed from a top surface thereof. Another via above the via is formed such that a bottom portion of the another via is in the recess of the via. In this way, no capture pad is needed between the via and the another via. Also, contact area between the via and the another via is enhanced.

公开(公告)号：US20220375838A1

公开(公告)日：2022-11-24

申请号：US17328666

申请日：2021-05-24

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Aniket PATIL ,  Zhijie WANG ,  Marcus HSU

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L23/535 ,  H01L23/28

Abstract: A package comprising a first integrated device comprising a first plurality of under bump metallization interconnects; a second integrated device comprising a second plurality of under bump metallization interconnects; a bridge coupled to the first integrated device and the second integrated device; an encapsulation layer at least partially encapsulating the first integrated device, the second integrated device, and the bridge; a metallization portion located over the first integrated device, the second integrated device, the bridge and the encapsulation layer, where the metallization portion includes at least one dielectric layer and a plurality of metallization interconnects; a first plurality of pillar interconnects coupled to the first plurality of under bump metallization interconnects, the first plurality of interconnects located in the encapsulation layer; and a second plurality of pillar interconnects coupled to the second plurality of under bump metallization interconnects, the second plurality of pillar interconnects located in the encapsulation layer.