公开(公告)号：US20150333072A1

公开(公告)日：2015-11-19

申请号：US14280213

申请日：2014-05-16

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Zhongze WANG ,  Daniel Wayne PERRY

IPC: H01L27/112 ,  G11C7/00 ,  G11C11/40

CPC classification number: H01L27/112 ,  G11C7/00 ,  G11C11/40 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

Abstract: An advanced metal-nitride-oxide-silicon (MNOS) multiple time programmable (MTP) memory is provided. In an example, an apparatus includes a two field effect transistor (2T field FET) metal-nitride-oxide-silicon (MNOS) MTP memory. The 2T field FET MNOS MTP memory can include an interlayer dielectric (ILD) oxide region that is formed on a well and separates respective gates of first and second transistors from the well. A control gate is located between the respective gates of the first and second transistors, and a silicon-nitride-oxide (SiN) region is located between a metal portion of the control gate and a portion of the ILD oxide region.

Abstract translation: 提供先进的金属氮化物 - 氧化物 - 硅（MNOS）多时间可编程（MTP）存储器。 在一个示例中，装置包括两个场效应晶体管（2T场FET）金属氮化物 - 氧化物 - 硅（MNOS）MTP存储器。 2T场FET MNOS MTP存储器可以包括形成在阱上的层间电介质（ILD）氧化物区域，并将第一和第二晶体管的相应栅极与阱分离。 控制栅极位于第一和第二晶体管的各个栅极之间，并且氮化硅 - 氧化物（SiN）区域位于控制栅极的金属部分和ILD氧化物区域的一部分之间。

公开(公告)号：US20150325515A1

公开(公告)日：2015-11-12

申请号：US14274470

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Kern RIM ,  Zhongze WANG

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5228 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor interconnects and methods for making semiconductor interconnects. An interconnect may include a first via of a first conductive material between a first conductive interconnect layer and a first middle of line (MOL) interconnect layer. The first MOL interconnect layer is on a first level. The first via is fabricated with a single damascene process. Such a semiconductor interconnect also includes a second via of a second conductive material between the first conductive interconnect layer and a second MOL interconnect layer. The second MOL interconnect layer is on a second level. The second via is fabricated with a dual damascene process. The first conductive material is different than the second conductive material.

Abstract translation: 用于半导体互连的半导体互连和方法。 互连可以包括在第一导电互连层和第一中间线（MOL）互连层之间的第一导电材料的第一通孔。 第一个MOL互连层位于第一层。 第一个通孔用单个镶嵌工艺制造。 这种半导体互连还包括在第一导电互连层和第二MOL互连层之间的第二导电材料的第二通孔。 第二个MOL互连层位于第二层。 第二个通孔用双镶嵌工艺制造。 第一导电材料与第二导电材料不同。

公开(公告)号：US20150262930A1

公开(公告)日：2015-09-17

申请号：US14206360

申请日：2014-03-12

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP ,  Zhongze WANG ,  Niladri MOJUMDER ,  Mustafa BADAROGLU

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/02167 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

Abstract translation: 系统和方法涉及一种集成电路，其包括由具有比铜的平均自由路径更低的示例性材料形成的减小的高度M1金属线，用于集成电路的片上电路元件的局部布线，其中降低的高度 M1金属线低于由铜形成的常规M1金属线的最小允许或允许的高度。 用于形成还原高度M1金属线的示例性材料包括钨（W），钼（Mo）和钌（Ru），其中这些示例性材料还具有比铜更低的电容和更低的RC延迟，同时提供高电迁移可靠性。

公开(公告)号：US20150115473A1

公开(公告)日：2015-04-30

申请号：US14064944

申请日：2013-10-28

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP ,  Zhongze WANG ,  Niladri Narayan MOJUMDER

IPC: H01L23/00 ,  H01L23/528

CPC classification number: H01L24/29 ,  H01L21/76251 ,  H01L21/8221 ,  H01L21/8258 ,  H01L23/528 ,  H01L24/83 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/267 ,  H01L2224/83948 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Methods for integrating heterogeneous channel material into a semiconductor device, and semiconductor devices that integrate heterogeneous channel material. A method for fabricating a semiconductor device includes processing a first substrate of a first material at a first thermal budget to fabricate a p-type device. The method further includes coupling a second substrate of a second material to the first substrate. The method also includes processing the second substrate to fabricate an n-type device at a second thermal budget that is less than the first thermal budget. The p-type device and the n-type device may cooperate to form a complementary device.

Abstract translation: 将异质沟道材料集成到半导体器件中的方法以及集成异构沟道材料的半导体器件。 一种制造半导体器件的方法包括以第一热预算处理第一材料的第一衬底以制造p型器件。 该方法还包括将第二材料的第二衬底耦合到第一衬底。 该方法还包括处理第二基板以在小于第一热预算的第二热预算下制造n型装置。 p型设备和n型设备可以协作以形成互补设备。

公开(公告)号：US20250087640A1

公开(公告)日：2025-03-13

申请号：US18465900

申请日：2023-09-12

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Zhongze WANG ,  Woo Tag KANG ,  Periannan CHIDAMBARAM

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H10B80/00

Abstract: Disclosed are packages that may include first and second substrates with first and second chips therebetween. The first chip may be a logic chip and the second chip may be a processing near memory (PNM) chip. The active side of the first chip may face the first substrate and the active side of the second chip may face the second substrate. The first chip may be encapsulated by a first mold, and the second chip may be encapsulated by a second mold. The first and/or the second molds may be thermally conductive. A third chip (e.g., a memory) may be on the second substrate opposite the second chip. The second substrate may include very short vertical connections that connect the active sides of the second and third chips.

公开(公告)号：US20240096790A1

公开(公告)日：2024-03-21

申请号：US17932500

申请日：2022-09-15

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Zhongze WANG

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5286

Abstract: Disclosed are integrated circuit structures with buried rails and backside metals for routing input signals to and/or output signals from one or more cells of the integrated circuit structures. Port landing-free connections to input ports and/or from output ports are enabled. As a result, signal routing flexibility is enhanced.

公开(公告)号：US20230115373A1

公开(公告)日：2023-04-13

申请号：US17450815

申请日：2021-10-13

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Zhongze WANG

IPC: G06F7/50 ,  G06F1/10

Abstract: Certain aspects provide an apparatus for performing machine learning tasks, and in particular, to computation-in-memory architectures. One aspect provides a method for in-memory computation. The method generally includes: accumulating, via each digital counter of a plurality of digital counters, output signals on a respective column of multiple columns of a memory, wherein a plurality of memory cells are on each of the multiple columns, the plurality of memory cells storing multiple bits representing weights of a neural network, wherein the plurality of memory cells of each of the multiple columns correspond to different word-lines of the memory; adding, via an adder circuit, output signals of the plurality of digital counters; and accumulating, via an accumulator, output signals of the adder circuit.

公开(公告)号：US20210124793A1

公开(公告)日：2021-04-29

申请号：US16666699

申请日：2019-10-29

Applicant: QUALCOMM Incorporated

Inventor： Zhongze WANG ,  Ye LU ,  Yandong GAO ,  Xiaochun ZHU ,  Xia LI

IPC: G06F17/16 ,  G06N3/063 ,  G11C11/412 ,  G11C11/419

Abstract: Certain aspects provide a circuit for in-memory computation. The circuit generally includes an in-memory computation array having a plurality of computation circuits, each of the computation circuits being configured to perform a dot product computation. In certain aspects, each of the computation circuits includes a memory cell, a capacitive element, a precharge transistor coupled between an output of the memory cell and the capacitive element, and a read transistor coupled between a read bit line (RBL) and the capacitive element.

公开(公告)号：US20210005230A1

公开(公告)日：2021-01-07

申请号：US16706429

申请日：2019-12-06

Applicant: QUALCOMM Incorporated

Inventor： Zhongze WANG ,  Xia LI ,  Ye LU ,  Yandong GAO

IPC: G11C7/06 ,  G11C7/10 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/4074 ,  G06N3/06

Abstract: A charge sharing Compute In Memory (CIM) may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a system voltage. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a read bit line. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal cap between XNOR and read bit line with a separate write bit line and write bit line bar.

公开(公告)号：US20160254056A1

公开(公告)日：2016-09-01

申请号：US14633793

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Xiao LU ,  Xiaonan CHEN ,  Zhongze WANG

IPC: G11C16/10 ,  G11C17/18 ,  G11C16/04 ,  G11C17/16

CPC classification number: G11C16/10 ,  G11C16/0466 ,  G11C17/146 ,  G11C17/16 ,  G11C17/18 ,  H01L27/11206 ,  H01L29/42348 ,  H01L29/7923

Abstract: A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side from the source terminal, a drain side charge trap in the dielectric region capable of programming the semiconductor device, and a source side charge trap in the dielectric region opposite the drain side charge trap and capable of programming the semiconductor device.

Abstract translation: 根据本公开的一些示例的用于一次可编程（OTP）存储器的半导体器件包括栅极，栅极下方的介电区域，介质区域下方的偏移并且偏移到一侧的源极端子，电介质下方的漏极端子 并且偏移到与源极端子相反的一侧，在能够编程半导体器件的电介质区域中的漏极侧电荷阱，以及与漏极侧电荷阱相对的电介质区域中的源极电荷陷阱，并且能够对半导体 设备。