公开(公告)号：US10649478B1

公开(公告)日：2020-05-12

申请号：US16436702

申请日：2019-06-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G05F1/567 ,  G05F1/56

Abstract: An integrated circuit component receives an input signal via an external signal conduction path during a first interval and transmits an output signal via the external signal conduction path during a second interval. The integrated circuit component terminates the input signal and the output signal within one or more termination elements having an impedance in accordance with a characteristic impedance of the external signal conduction path to obviate signal termination within another integrated circuit component to which the output signal is destined and from which the input signal is sourced.

公开(公告)号：US20190266115A1

公开(公告)日：2019-08-29

申请号：US16290375

申请日：2019-03-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G11C7/10 ,  G06F13/16 ,  G11C5/04

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

公开(公告)号：US10345836B1

公开(公告)日：2019-07-09

申请号：US15221854

申请日：2016-07-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G05F1/56 ,  G05F1/567

Abstract: An integrated circuit component receives an input signal via an external signal conduction path during a first interval and transmits an output signal via the external signal conduction path during a second interval. The integrated circuit component terminates the input signal and the output signal within one or more termination elements having an impedance in accordance with a characteristic impedance of the external signal conduction path to obviate signal termination within another integrated circuit component to which the output signal is destined and from which the input signal is sourced.

公开(公告)号：US10339999B2

公开(公告)日：2019-07-02

申请号：US16011539

申请日：2018-06-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C7/02 ,  G11C29/52 ,  G11C29/04

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US09916873B2

公开(公告)日：2018-03-13

申请号：US15013032

申请日：2016-02-02

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  John Eric Linstadt

IPC: G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C5/04 ,  G11C5/063 ,  G11C7/10 ,  G11C7/22

Abstract: A memory module uses dynamic data buffers for providing extended capacity for computing systems. The memory module comprises an external interface having a first set of data pins and a second set of data pins. The memory module includes a first set of memory chips and a second set of memory chips. The memory module includes a first registering clock driver to control the first set of memory chips and a second registering clock driver to control the second set of memory chips. The memory module further includes a first data buffer to connect the first set of memory chips to the first set of data pins and a second data buffer to connect the second set of memory chips to the second set of data pins.

公开(公告)号：US20180039416A1

公开(公告)日：2018-02-08

申请号：US15642860

申请日：2017-07-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G06F3/06 ,  G11C11/4091

CPC classification number: G06F3/064 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0655 ,  G06F3/0673 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.

公开(公告)号：US20170324019A1

公开(公告)日：2017-11-09

申请号：US15478757

申请日：2017-04-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Carl W. Werner

IPC: H01L39/02

CPC classification number: H03K3/38 ,  H03K19/017509 ,  H03K19/195

Abstract: In an integrated-circuit component having a signal transmitter receives a transmitter power supply that cycles periodically between power-off and power-on voltage levels to define a sequence of enable intervals during which the signal transmitter is to output voltage levels corresponding to respective transmit data bits onto an external signaling link. The signal transmitter generates, at the start of each output-enable interval, an initial nonzero voltage having a first polarity across conductors of the external signaling link, and then conditionally transitions the initial nonzero voltage to a second nonzero voltage according to whether the transmit data bit corresponding to the output-enable interval has a predetermined one of two binary states, the second nonzero voltage having a polarity opposite the first polarity.

公开(公告)号：US09703483B2

公开(公告)日：2017-07-11

申请号：US14441810

申请日：2013-11-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G06F3/06 ,  G11C8/12 ,  G06F12/06

CPC classification number: G06F3/0604 ,  G06F3/0635 ,  G06F3/0673 ,  G06F12/06 ,  G06F2212/1048 ,  G11C8/12 ,  G11C2207/107

Abstract: A multiple memory rank selection method and system assigns, based at least in part on decoding an assignment signal in a second command/address signal, a first terminal of a memory device to receive a first command/address signal and a second terminal of the memory device to receive the second command/address signal or assigns the first terminal of the memory device to receive the second command/address signal and the second terminal of the memory device to receive the first command/address signal. The multiple memory selection method and system decodes a selection signal encoded in the first command/address signal and enables the memory device based at least in part on the assignment signal and the selection signal.

公开(公告)号：US20140115296A1

公开(公告)日：2014-04-24

申请号：US14058081

申请日：2013-10-18

Applicant: Rambus Inc.

Inventor： Trung Diep ,  John Eric Linstadt ,  J. James Tringali ,  Hongzhong Zheng ,  Brent Steven Haukness

IPC: G06F12/10

CPC classification number: G06F12/0238 ,  G06F2212/7204 ,  G06F2212/7211 ,  G11C13/0028 ,  G11C13/0035 ,  G11C13/0069 ,  G11C29/50008 ,  G11C2029/0409 ,  G11C2213/72 ,  G11C2213/79

Abstract: A method of operating a memory device that includes groups of memory cells is presented. The groups include a first group of memory cells. Each one of the groups has a respective physical address and is initially associated with a respective logical address. The device also includes an additional group of memory cells that has a physical address but is not initially associated with a logical address. In the method, a difference in the future endurance between the first group of memory cells and the additional group of memory cells is identified. When the difference in the future endurance between the first group and the additional group exceeds a predetermined threshold difference, the association between the first group and the logical address initially associated with the first group is ended and the additional group is associated with the logical address that was initially associated with the first group.

Abstract translation: 提出了一种操作包括存储器单元组的存储器件的方法。 这些组包括第一组记忆单元。 组中的每一个具有相应的物理地址，并且最初与相应的逻辑地址相关联。 该设备还包括具有物理地址但不是最初与逻辑地址相关联的附加组的存储器单元。 在该方法中，识别第一组存储器单元和附加的存储单元组之间的未来耐久性的差异。 当第一组和附加组之间的未来耐久性的差异超过预定阈值差时，第一组与最初与第一组相关联的逻辑地址之间的关联结束，并且附加组与逻辑地址相关联， 最初与第一组有关。

公开(公告)号：US20240313135A1

公开(公告)日：2024-09-19

申请号：US18623868

申请日：2024-04-01

Applicant: Rambus Inc.

Inventor： Yohan Frans ,  Simon Li ,  John Eric Linstadt ,  Jun Kim

IPC: H01L31/0236 ,  G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F13/16 ,  G06F13/372

CPC classification number: H01L31/02366 ,  G06F3/0613 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1684 ,  G06F13/372 ,  G06F12/00 ,  G06F13/16 ,  Y02D10/00

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.