公开(公告)号：US11709736B2

公开(公告)日：2023-07-25

申请号：US17354268

申请日：2021-06-22

Applicant: Rambus Inc.

Inventor： Kenneth L. Wright ,  Frederick A. Ware

IPC: G06F11/00 ,  G06F11/14 ,  H01L23/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/40 ,  H01L25/065 ,  H01L25/10

CPC classification number: G06F11/142 ,  G06F3/0617 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F11/00 ,  G06F13/1673 ,  G06F13/4068 ,  H01L24/00 ,  H01L24/17 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  G06F11/1423 ,  G06F2201/805 ,  G06F2201/82 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/4824 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/85399

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.

公开(公告)号：US11625346B2

公开(公告)日：2023-04-11

申请号：US17715379

申请日：2022-04-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright

IPC: G06F11/00 ,  G06F13/16 ,  G06F11/07 ,  G06F13/40 ,  G06F11/20 ,  G06F11/16 ,  G06F11/10

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

公开(公告)号：US20220350763A1

公开(公告)日：2022-11-03

申请号：US17748762

申请日：2022-05-19

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G11C5/04 ,  G11C7/10 ,  G06F13/16

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

公开(公告)号：US11211114B2

公开(公告)日：2021-12-28

申请号：US16503189

申请日：2019-07-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  John E. Linstadt ,  Thomas J. Giovannini ,  Scott C. Best ,  Kenneth L. Wright

IPC: G11C5/02 ,  G11C11/4093 ,  G11C5/06 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/00 ,  H01L25/065 ,  H01L25/10 ,  G11C11/4096 ,  H01L25/18 ,  G11C7/10 ,  G11C8/12 ,  H01L23/00

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

公开(公告)号：US11164622B2

公开(公告)日：2021-11-02

申请号：US17101574

申请日：2020-11-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C7/02 ,  G11C29/52 ,  G11C29/04

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US20210174863A1

公开(公告)日：2021-06-10

申请号：US17101574

申请日：2020-11-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C29/52 ,  G11C7/02 ,  G11C11/4096 ,  G06F11/10 ,  G11C29/04

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US20210118480A1

公开(公告)日：2021-04-22

申请号：US17089899

申请日：2020-11-05

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/00 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0895 ,  G11C5/04 ,  G11C14/00 ,  G06F12/02

Abstract: A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.

公开(公告)号：US10678719B2

公开(公告)日：2020-06-09

申请号：US15761746

申请日：2016-09-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright ,  John Eric Linstadt ,  Craig Hampel

IPC: G06F13/16 ,  G06F12/0868 ,  G06F12/0888 ,  G11C7/10 ,  G06F3/06 ,  G06F11/10 ,  G06F12/0895 ,  G06F13/28 ,  G11C29/52

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.

公开(公告)号：US10650881B2

公开(公告)日：2020-05-12

申请号：US16440015

申请日：2019-06-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C7/02 ,  G11C29/52 ,  G11C29/04

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US20200050562A1

公开(公告)日：2020-02-13

申请号：US16548714

申请日：2019-08-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright

IPC: G06F13/16 ,  G06F11/07 ,  G06F13/40

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.