公开(公告)号：US09299569B2

公开(公告)日：2016-03-29

申请号：US14801798

申请日：2015-07-16

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Kentaro Saito ,  Hiraku Chakihara

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/40

CPC classification number: H01L21/28282 ,  H01L21/02164 ,  H01L21/0217 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/401 ,  H01L29/42344 ,  H01L29/66833

Abstract: The present invention improves the performance of a semiconductor device. In a manufacturing method of a semiconductor device, sacrificial oxide films are formed over the side surface of a control gate electrode formed in a memory cell region, the surface of a cap insulating film formed in the memory cell region, and the surface of the part, which remains in a peripheral circuit region, of an insulating film. The step of forming the sacrificial oxide films includes the steps of: oxidizing the side surface of the control gate electrode by a thermal oxidation method; and oxidizing the surface of the cap insulating film and the surface of the part, which remains in the peripheral circuit region, of the insulating film by an ISSG oxidation method.

Abstract translation: 本发明改进了半导体器件的性能。 在半导体器件的制造方法中，在形成在存储单元区域中的控制栅电极的侧表面上形成牺牲氧化物膜，形成在存储单元区域中的帽绝缘膜的表面和部件的表面 ，其保留在绝缘膜的周边电路区域中。 形成牺牲氧化膜的步骤包括以下步骤：通过热氧化法氧化控制栅电极的侧表面; 并通过ISSG氧化法氧化绝缘膜上的帽绝缘膜的表面和保留在外围电路区域中的部分的表面。

公开(公告)号：US11276702B2

公开(公告)日：2022-03-15

申请号：US16854399

申请日：2020-04-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki Kawashima

IPC: H01L31/028 ,  H01L27/088 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  G11C5/02

Abstract: Fins lined up in a Y direction, a control gate electrode and a memory gate electrode each extending in the Y direction so as to straddle the fins, a plurality of first plugs electrically connected with a drain region formed in each of the fins, and a plurality of second plugs electrically connected with a source region formed in each of the fins are formed. Here, a N-th plug of the plurality of first plugs lined up in the Y direction is coupled with each of (2N−1)-th and 2N-th fins in the Y direction. Also, a N-th plug of the plurality of second plugs lined up in the Y direction is coupled with each of 2N-th and (2N+1)-th fins in the Y direction.

公开(公告)号：US11063055B2

公开(公告)日：2021-07-13

申请号：US16676114

申请日：2019-11-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki Kawashima

IPC: H01L27/11534 ,  H01L27/11526 ,  H01L21/3213 ,  H01L21/311

Abstract: A second gate dielectric film material and a memory gate electrode material are formed on a semiconductor substrate. The memory gate electrode material and the second gate dielectric film material formed in a peripheral circuit forming region are removed, and a part of each of the memory gate electrode material and the second gate dielectric film material is left in the memory cell forming region. Thereafter, in a state that the semiconductor substrate in the memory cell forming region is covered with a part of each of the memory gate electrode material and the second gate dielectric film material, heat treatment is performed to the semiconductor substrate to form a third gate dielectric film on the semiconductor substrate located in the peripheral circuit forming region. Thereafter, a memory gate electrode and a second gate dielectric film are formed.

公开(公告)号：US10978385B2

公开(公告)日：2021-04-13

申请号：US16655606

申请日：2019-10-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC: H01L29/66 ,  H01L23/522 ,  H01L27/11517 ,  H01L21/768 ,  H01L23/532 ,  H01L21/762 ,  H01L49/02 ,  H01L27/11573 ,  H01L29/94 ,  H01L27/12 ,  H01L27/08 ,  H01L27/06

Abstract: This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.

公开(公告)号：US10854730B2

公开(公告)日：2020-12-01

申请号：US16447457

申请日：2019-06-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Digh Hisamoto ,  Yoshiyuki Kawashima

IPC: H01L29/792 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L27/11565 ,  H01L27/11568 ,  H01L21/28

Abstract: A part of the semiconductor substrate is processed to form fins protruding from the upper surface of the semiconductor substrate. Next, an interlayer insulating film is formed on the semiconductor substrate including the fin FA, and an opening is formed in the interlayer insulating film. Next, a dummy pattern including the dummy material and the insulating film is formed in the opening in a self-aligned manner. Thereafter, the dummy pattern is replaced with a memory gate electrode, a control gate electrode, and the like.

公开(公告)号：US09349743B2

公开(公告)日：2016-05-24

申请号：US14804305

申请日：2015-07-20

Applicant: Renesas Electronics Corporation

Inventor： Nobuto Nakanishi ,  Yoshiyuki Kawashima ,  Akio Nishida

IPC: H01L21/28 ,  H01L27/115 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/51 ,  H01L21/3213 ,  H01L29/45 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/31053 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/456 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659

Abstract: To provide a semiconductor device having improved reliability. A semiconductor device is provided forming a control gate electrode for memory cell on a semiconductor substrate via a first insulating film; forming a memory gate electrode for memory cell, which is adjacent to the control gate electrode, on the semiconductor substrate via a second insulating film having a charge storage portion; forming n− type semiconductor regions for source or drain in the semiconductor substrate by ion implantation; forming sidewall spacers on the side wall of the control gate electrode and the memory gate electrode; forming n+ type semiconductor regions for source or drain in the semiconductor substrate by ion implantation; and removing an upper portion of the second insulating film present between the control gate electrode and the memory gate electrode. A removal length of the second insulating film is larger than the depth of the n+ type semiconductor regions.

Abstract translation: 提供具有提高的可靠性的半导体器件。 提供一种通过第一绝缘膜在半导体衬底上形成用于存储单元的控制栅电极的半导体器件; 通过具有电荷存储部分的第二绝缘膜，在半导体衬底上形成与控制栅电极相邻的用于存储单元的存储栅电极; 通过离子注入在半导体衬底中形成用于源极或漏极的n-型半导体区域; 在控制栅电极和存储栅电极的侧壁上形成侧壁间隔物; 通过离子注入在半导体衬底中形成用于源极或漏极的n +型半导体区域; 以及去除存在于控制栅电极和存储栅电极之间的第二绝缘膜的上部。 第二绝缘膜的去除长度大于n +型半导体区域的深度。

公开(公告)号：US09231115B2

公开(公告)日：2016-01-05

申请号：US14308667

申请日：2014-06-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki Kawashima ,  Koichi Toba

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L29/40

CPC classification number: H01L29/792 ,  H01L21/02214 ,  H01L21/26513 ,  H01L27/11573 ,  H01L29/401 ,  H01L29/42344 ,  H01L29/66833

Abstract: An improvement is achieved in the performance of semiconductor device including a nonvolatile memory. In a split-gate nonvolatile memory, between a memory gate electrode and a p-type well and between a control gate electrode and the memory gate electrode, an insulating film is formed. Of the insulating film, the portion between the lower surface of the memory gate electrode and the upper surface of a semiconductor substrate has silicon oxide films, and a silicon nitride film interposed between the silicon oxide films. Of the insulating film, the portion between a side surface of the control gate electrode and a side surface of the memory gate electrode is formed of a silicon oxide film, and does not have the silicon nitride film.

公开(公告)号：US12206008B2

公开(公告)日：2025-01-21

申请号：US17513404

申请日：2021-10-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki Kawashima ,  Masao Inoue

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/792

Abstract: A memory cell which is a non-volatile memory cell includes a gate insulating film having a charge storage layer capable of retaining charge and a memory gate electrode formed on the gate insulating film. The charge storage layer includes a first insulating film containing hafnium and silicon and a second insulating film formed on the first insulating film and containing hafnium and silicon. Here, a hafnium concentration of the first insulating film is lower than a hafnium concentration of the second insulating film, and a bandgap of the first insulating film is larger than a bandgap of the second insulating film.

公开(公告)号：US10388660B2

公开(公告)日：2019-08-20

申请号：US15796815

申请日：2017-10-29

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC: H01L29/78 ,  H01L27/1157 ,  G11C16/10 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  G11C16/26 ,  H01L23/528 ,  G11C16/04 ,  G11C16/34

Abstract: A semiconductor device in which the cell size is small and disturbance in reading operation is suppressed, and a method for manufacturing the semiconductor device. A first memory cell has a first memory transistor. A second memory cell has a second memory transistor. A control gate is shared by the first memory cell and the second memory cell. In plan view, the control gate is sandwiched between a first memory gate of the first memory transistor and a second memory gate of the second memory transistor.

公开(公告)号：US10217872B2

公开(公告)日：2019-02-26

申请号：US15626092

申请日：2017-06-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Masao Inoue ,  Atsushi Yoshitomi

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L27/1157 ,  H01L27/11573

Abstract: A memory cell includes a control gate electrode and a memory gate electrode. The control gate electrode is formed over the upper surface and the sidewall of a fin FA including apart of a semiconductor substrate. The memory gate electrode is formed over one side surface of the control gate electrode and the upper surface and the sidewall of the fin through an ONO film, in a position adjacent to the one side surface of the control gate electrode. Further, the control gate electrode and the memory gate electrode are formed of n-type polycrystalline silicon. A first metal film is provided between the gate electrode and the control gate electrode. A second metal film is provided between the ONO film and the memory gate electrode. A work function of the first metal film is greater than a work function of the second metal film.