公开(公告)号：US06969654B1

公开(公告)日：2005-11-29

申请号：US09727714

申请日：2000-11-28

申请人： Tuan Duc Pham ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Angela T. Hui ,  Dawn Hopper

发明人： Tuan Duc Pham ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Angela T. Hui ,  Dawn Hopper

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L23/552 ,  H01L27/115

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L23/552 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of preventing UV charging of flash NVROM cells during fabrication and a device thereby formed. During device fabrication, a UV blocking layer is deposited over the floating gates. The UV blocking layer substantially blocks UV from entering the gate regions so as to prevent electron mobility sufficient to render the cells unprogrammable or unerasable. The reduced electron migration during processing of the NVROM leads to increased yield and reliability of the devices.

摘要翻译： 一种在制造期间防止闪存NVROM单元的紫外线充电的方法和由此形成的装置。 在器件制造期间，在阻挡层上沉积UV阻挡层。 UV阻挡层基本上阻止UV进入栅极区域，以便防止电子迁移率足以使电池不可编程或不可擦除。 在NVROM处理期间减少的电子迁移导致器件的产量和可靠性的提高。

公开(公告)号：US06808996B1

公开(公告)日：2004-10-26

申请号：US09376659

申请日：1999-08-18

申请人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

发明人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.

摘要翻译： 制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。 然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。 然后将掺杂剂注入漏区。 在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

公开(公告)号：US06635943B1

公开(公告)日：2003-10-21

申请号：US09533617

申请日：2000-03-22

申请人： Angela T. Hui ,  Tuan Duc Pham ,  Richard J. Huang ,  Mark T. Ramsbey ,  Lu You

发明人： Angela T. Hui ,  Tuan Duc Pham ,  Richard J. Huang ,  Mark T. Ramsbey ,  Lu You

IPC分类号： H01L2900

CPC分类号： H01L21/823425 ,  H01L21/76819 ,  H01L21/76837

摘要： A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The interlayer dielectric is capable of gap filling while using only species of relatively low mobility. The method and system also include planarizing a surface of the interlayer dielectric.

摘要翻译： 公开了一种用于将半导体器件的下层与半导体器件的上层绝缘的方法和系统。 该方法和系统包括在下层上提供层间电介质。 层间电介质能够间隙填充，同时仅使用相对较低迁移率的物质。 该方法和系统还包括平坦化层间电介质的表面。

公开(公告)号：US06583009B1

公开(公告)日：2003-06-24

申请号：US10178106

申请日：2002-06-24

申请人： Angela T. Hui ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Sameer Haddad ,  Yu Sun

发明人： Angela T. Hui ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Sameer Haddad ,  Yu Sun

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115 ,  Y10S438/952

摘要： The present invention relates to a method of forming a stacked gate flash memory cell and comprises forming a tunnel oxide layer, a first conductive layer, an interpoly dielectric layer, and a second conductive layer in succession over a semiconductor substrate. The method further comprises forming a sacrificial layer over the second conductive layer, and patterning the sacrificial layer to form a sacrificial layer feature having at least one lateral sidewall edge associated therewith. A sidewall spacer is then formed against the lateral sidewall edge of the sacrificial layer, wherein the spacer has a width associated therewith, and the patterned sacrificial layer feature is removed. Finally, the second conductive layer, the interpoly dielectric and the first conductive layer are patterned using the spacer as a hard mask, and defining the stacked gate, wherein a width of the stacked gate is a function of the spacer width.

摘要翻译： 本发明涉及一种形成层叠栅极闪存单元的方法，包括在半导体衬底上连续形成隧道氧化物层，第一导电层，多晶硅间介质层和第二导电层。 该方法还包括在第二导电层上形成牺牲层，以及图案化牺牲层以形成具有与其相关联的至少一个侧向侧壁边缘的牺牲层特征。 然后在牺牲层的横向侧壁边缘上形成侧壁间隔物，其中间隔件具有与其相关联的宽度，并且去除图案化的牺牲层特征。 最后，使用间隔物作为硬掩模来图案化第二导电层，多晶硅间电介质和第一导电层，并且限定堆叠栅极，其中堆叠栅极的宽度是间隔物宽度的函数。

公开(公告)号：US06548334B1

公开(公告)日：2003-04-15

申请号：US10179061

申请日：2002-06-24

申请人： Tuan Duc Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui

发明人： Tuan Duc Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui

IPC分类号： H01L21337

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543

摘要： A method of fabricating an improved flash memory device having core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insulating layer, the protective layer and oxide layer into the substrate to create source and drain regions, without using a self aligned etch. The flash memory device has an intermetallic dielectric layer placed over the core stacks and the periphery stacks. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device. The use of a high energy dopant implant to pass through dopant through the insulating layer, the protective layer and the oxide layer into the substrate without the use of a self aligned source etch, reduces damage to the core stacks and periphery stacks caused by various etches during the production of the flash memory device and provides insulation to reduce unwanted current between the tungsten plug and the stacks.

摘要翻译： 一种制造具有由氧化层，保护层和绝缘层保护的芯堆叠和外围堆叠的改进的闪存器件的方法。 使用高能掺杂剂注入来使掺杂剂通过绝缘层，保护层和氧化物层进入衬底以产生源区和漏区，而不使用自对准蚀刻。 闪存器件具有放置在芯堆叠和外围堆叠体上的金属间介电层。 将钨塞放置在金属间介电层中以提供与闪存器件的漏极的电连接。 使用高能掺杂剂注入物通过掺杂剂通过绝缘层，保护层和氧化物层进入衬底而不使用自对准源蚀刻，减少了由各种蚀刻引起的芯堆叠和外围堆叠的损坏 在制造闪速存储器件期间提供绝缘以减少钨插头和堆叠之间的不必要的电流。

公开(公告)号：US06528398B1

公开(公告)日：2003-03-04

申请号：US09775084

申请日：2001-02-01

申请人： Kouros Ghandehari ,  Bhanwar Singh ,  Angela T. Hui

发明人： Kouros Ghandehari ,  Bhanwar Singh ,  Angela T. Hui

IPC分类号： H01L2176

CPC分类号： G03F7/094 ,  G03F7/405 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/76816

摘要： An exemplary embodiment described in the disclosure relates to a method of fabricating an integrated circuit which includes providing a bulk layer over a semiconductor substrate, providing an imaging layer over the bulk layer, imaging the imaging layer to expose portions of the imaging layer, removing the exposed portions of the imaging layer, etching the bulk layer at locations where exposed portions of the imaging layer were removed to provide at least one aperture in the bulk layer, and silylating the bulk layer.

摘要翻译： 本公开中描述的示例性实施例涉及一种制造集成电路的方法，其包括在半导体衬底上提供体层，在体层上提供成像层，使成像层成像以暴露成像层的部分，去除 成像层的暴露部分，在去除成像层的暴露部分的位置处蚀刻体层以在本体层中提供至少一个孔，以及使体层甲硅烷化。

公开(公告)号：US06514867B1

公开(公告)日：2003-02-04

申请号：US09817586

申请日：2001-03-26

申请人： Angela T. Hui ,  Bhanwar Singh

发明人： Angela T. Hui ,  Bhanwar Singh

IPC分类号： H01L2100

CPC分类号： H01L21/31144

摘要： An exemplary method is described which forms narrow trench lines having a critical dimension which is smaller than the critical dimension possible using conventional lithographic techniques. This method can include providing a hard mask over a layer of material in which a trench line is to be formed; etching the hard mask with a first critical dimension at the top of the hard mask and a second critical dimension at the bottom of the hard mask; and etching a trench line using the hard mask to transfer the second critical dimension to the trench line.

摘要翻译： 描述了一种示例性的方法，其形成具有小于使用常规光刻技术的临界尺寸的临界尺寸的窄沟槽线。 该方法可以包括在要形成沟槽线的材料层上提供硬掩模; 在硬掩模的顶部以第一临界尺寸蚀刻硬掩模，在硬掩模的底部蚀刻第二临界尺寸; 以及使用所述硬掩模蚀刻沟槽线以将所述第二临界尺寸转移到所述沟槽线。

公开(公告)号：US06514849B1

公开(公告)日：2003-02-04

申请号：US09824420

申请日：2001-04-02

申请人： Angela T. Hui ,  Bhanwar Singh

发明人： Angela T. Hui ,  Bhanwar Singh

IPC分类号： H01L214763

CPC分类号： H01L21/31144

摘要： An exemplary method of forming contact holes includes providing a photoresist pattern over an anti-reflective coating (ARC) layer where the ARC layer is deposited over a layer of material; etching the ARC layer according to the photoresist pattern to form ARC features; forming spacers on lateral sides of the ARC features; and etching trench lines using the spacers and ARC features as hard mask to define portions of the layer of material which are etched.

摘要翻译： 形成接触孔的示例性方法包括在抗反射涂层（ARC）层上提供光致抗蚀剂图案，其中ARC层沉积在材料层上; 根据光致抗蚀剂图案蚀刻ARC层以形成ARC特征; 在ARC特征的侧面上形成间隔物; 并且使用间隔物和ARC特征蚀刻沟槽线作为硬掩模以限定蚀刻的材料层的部分。

公开(公告)号：US06432618B1

公开(公告)日：2002-08-13

申请号：US09535255

申请日：2000-03-23

申请人： Angela T. Hui ,  Jusuke Ogura

发明人： Angela T. Hui ,  Jusuke Ogura

IPC分类号： H01L21302

CPC分类号： H01L21/823462 ,  H01L21/31138

摘要： A method for forming high quality oxide layers having different thicknesses by eliminating descum induced defects. The method includes forming an oxide layer, masking the oxide layer with a photoresist layer, developing the photoresist layer to expose a region of the oxide layer. The substrate is then descummed to remove any residue resulting from the development of the photoresist. Following the descum process, the substrate is rinsed in water. The oxide layer is then etched, and the remaining photoresist is stripped before another layer of oxide is grown on the substrate.

摘要翻译： 一种通过消除除去诱导缺陷来形成具有不同厚度的高质量氧化物层的方法。 该方法包括形成氧化物层，用光致抗蚀剂层掩蔽氧化物层，显影光致抗蚀剂层以暴露氧化物层的区域。 然后除去基材以除去由光致抗蚀剂显影产生的残留物。 在除去过程之后，将基底在水中漂洗。 然后蚀刻氧化物层，并且在衬底上生长另一层氧化物之前剥离剩余的光致抗蚀剂。

公开(公告)号：US6103593A

公开(公告)日：2000-08-15

申请号：US23836

申请日：1998-02-13

申请人： Angela T. Hui ,  Hung-Sheng Chen ,  Unsoon Kim

发明人： Angela T. Hui ,  Hung-Sheng Chen ,  Unsoon Kim

IPC分类号： H01L21/762 ,  H01L21/768 ,  H01L21/76 ,  H01L21/44

CPC分类号： H01L21/76802 ,  H01L21/76237 ,  H01L21/76834 ,  Y10S438/97

摘要： A method for providing at least one contact on a semiconductor is disclosed. The semiconductor includes a plurality of isolation structures. The method and system include providing an etch-stop layer in direct contact with the semiconductor, providing a dielectric layer over the etch-stop layer, and etching through the dielectric layer and a portion of the etch-stop layer. A portion of the semiconductor in proximity with one of the plurality of isolation structures is not exposed during the etch.

摘要翻译： 公开了一种在半导体上提供至少一个接触的方法。 半导体包括多个隔离结构。 该方法和系统包括提供与半导体直接接触的蚀刻停止层，在蚀刻停止层上方提供介电层，以及蚀刻穿过介电层和蚀刻停止层的一部分。 在蚀刻期间，与多个隔离结构之一接近的半导体的一部分不暴露。