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    Nonvolatile memory device including erase transistors
    31.
    发明授权
    Nonvolatile memory device including erase transistors 有权

    公开(公告)号：US11430802B2

    公开(公告)日：2022-08-30

    申请号：US17155525

    申请日：2021-01-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chanho Kim

    IPC: H01L27/11 ,  G11C16/00 ,  H01L27/11573 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L23/522

    Abstract: A nonvolatile memory device includes bitlines, a source line, cell channel structures, a gate electrode structure, erase channel structures and an erase selection line. The bitlines are disposed at a first end portion of a cell region, arranged in a first horizontal direction and extend in a second horizontal direction. The source line is disposed at a second end portion of the cell region and extend in the second horizontal direction. The cell channel structures are disposed in a cell string area of the cell region and are respectively connected between the bitlines and the source line. The erase channel structures are disposed in a contact area of the cell region and respectively connected between the bitlines and the source line. The erase channel structures include erase transistors. The erase selection line is disposed in the contact area to form a gate electrode of the erase transistors.

    Integrated circuit device
    32.
    发明授权
    Integrated circuit device 有权

    公开(公告)号：US11329057B2

    公开(公告)日：2022-05-10

    申请号：US16944733

    申请日：2020-07-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chanho Kim ,  Dongku Kang ,  Daeseok Byeon

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/112 ,  H01L27/11585 ,  H01L27/108 ,  H01L27/24

    Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

    Memory device
    33.
    发明授权
    Memory device 有权

    公开(公告)号：US11289500B2

    公开(公告)日：2022-03-29

    申请号：US17001035

    申请日：2020-08-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwa Yun ,  Pansuk Kwak ,  Chanho Kim ,  Dongku Kang

    IPC: G11C16/04 ,  H01L27/11573 ,  H01L27/1157 ,  G11C16/08 ,  G11C7/18 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

    Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in the first direction, and second pads different from the first pads, wherein the cell contacts are connected to the wordlines in the first pads, wherein the number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region, and wherein the memory cell region includes a first metal pad and the peripheral circuit region includes a second metal pad, and the memory cell region and the peripheral circuit region are vertically connected to each other by the first metal pad and the second metal pad.

    Memory device
    35.
    发明授权
    Memory device 有权

    公开(公告)号：US11227860B2

    公开(公告)日：2022-01-18

    申请号：US16942854

    申请日：2020-07-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jooyong Park ,  Chanho Kim ,  Daeseok Byeon

    IPC: H01L23/522 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00

    Abstract: A memory device includes a memory cell chip, a peripheral circuit chip, and a routing wire. The memory cell chip includes a memory cell array disposed on a first substrate, and a first metal pad on a first uppermost metal layer. The peripheral circuit chip includes circuit devices disposed on a second substrate, and a second metal pad on a second uppermost metal layer of the peripheral circuit chip. The memory cell chip and the peripheral circuit chip are vertically connected to each other by the first metal pad and the second metal pad in a bonding area. The routing wire is electrically connected to the peripheral circuit and is disposed in the first uppermost metal layer or the second uppermost metal layer and is disposed in a non-bonding area in which the memory cell chip and the peripheral circuit chip are not electrically connected to each other.

    MEMORY DEVICE, MEMORY SYSTEM AND AUTONOMOUS DRIVING APPARATUS
    36.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM AND AUTONOMOUS DRIVING APPARATUS 有权

    公开(公告)号：US20210124527A1

    公开(公告)日：2021-04-29

    申请号：US16892574

    申请日：2020-06-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taehong Kwon ,  Daeseok Byeon ,  Chanho Kim ,  Taehyo Kim

    IPC: G06F3/06 ,  G06F13/16 ,  G05D1/00

    Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data according to an M-bit data access scheme, where N is a natural number, and a first peripheral circuit for controlling the first memory cells and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data according to an M-bit data access scheme, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells and disposed below the second memory cell array, the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    39.
    发明申请
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20250031376A1

    公开(公告)日：2025-01-23

    申请号：US18582722

    申请日：2024-02-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junil Lee ,  Yongjun Kim ,  Chanho Kim ,  Sangwan Nam ,  Ryoongbin Lee

    IPC: H10B43/40 ,  G11C16/30 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

    Abstract: A semiconductor device may include a first semiconductor structure including a substrate, an active region in the substrate, a device isolation region defining the active region, and a capacitor structure on the device isolation region and vertically overlapping the device isolation region. The capacitor structure may include a first electrode structure extending in a first direction and including first capacitor electrodes stacked in the first direction, a second electrode structure including second capacitor electrodes stacked in the first direction, and a first insulating structure between the first electrode structure and the second electrode structure. Each of the first capacitor electrodes and the second capacitor electrodes are alternately arranged and spaced apart from each other in a second direction parallel to an upper surface of the substrate, extend in a third direction perpendicular to the first direction and the second direction, and has a plate shape.

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