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    Semiconductor memory device and semiconductor package
    31.
    发明授权
    Semiconductor memory device and semiconductor package 有权
    半导体存储器件和半导体封装

    公开(公告)号：US09390784B2

    公开(公告)日：2016-07-12

    申请号：US14290088

    申请日：2014-05-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Min-hee Cho ,  Satoru Yamada ,  Sang-ho Shin ,  Sung-sam Lee

    IPC: G11C11/406 ,  G11C7/04 ,  G11C16/34

    CPC classification number: G11C11/40626 ,  G11C7/04 ,  G11C16/3418 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

    Abstract: A semiconductor memory device includes: a memory unit including a first memory sub region including a first memory cell and a second memory sub region including a second memory cell; a temperature information obtaining unit that obtains temperature information; a temperature estimation unit that estimates a first temperature of the first memory sub region and a second temperature of the second memory sub region based on the temperature information; a first sub region control unit that controls the first memory sub region based on the first temperature; and a second sub region control unit that controls the second memory sub region based on the second temperature.

    Abstract translation: 半导体存储器件包括：存储单元，包括包括第一存储单元的第一存储器子区域和包括第二存储器单元的第二存储器子区域; 获取温度信息的温度信息获取单元; 温度估计单元，其基于所述温度信息来估计所述第一存储器子区域的第一温度和所述第二存储器子区域的第二温度; 第一子区域控制单元，其基于第一温度来控制第一存储器子区域; 以及第二子区域控制单元，其基于第二温度来控制第二存储器子区域。

    Semiconductor device
    32.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08947950B2

    公开(公告)日：2015-02-03

    申请号：US13770150

    申请日：2013-02-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyo-Suk Chae ,  Satoru Yamada

    IPC: G11C7/00 ,  H01L29/78 ,  G11C11/4094 ,  G11C11/4096

    CPC classification number: H01L29/7816 ,  G11C7/00 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/005

    Abstract: A semiconductor memory device includes a bit line connected to a memory cell; an input/output line configured to input a data signal to the memory cell during a writing operation and to output a data signal stored in the memory cell during a reading operation; and a column select transistor including a first source/drain connected to the bit line and a second source/drain connected to the input/output line, wherein a resistance of the first source/drain is smaller than a resistance of the second source/drain.

    Abstract translation: 半导体存储器件包括连接到存储器单元的位线; 输入/输出线，被配置为在写入操作期间将数据信号输入到存储器单元，并且在读取操作期间输出存储在存储单元中的数据信号; 以及列选择晶体管，其包括连接到所述位线的第一源极/漏极和连接到所述输入/输出线的第二源极/漏极，其中所述第一源极/漏极的电阻小于所述第二源极/漏极的电阻 。

    Semiconductor devices including semiconductor pattern
    34.
    发明授权
    Semiconductor devices including semiconductor pattern 有权

    公开(公告)号：US11581316B2

    公开(公告)日：2023-02-14

    申请号：US17092593

    申请日：2020-11-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Huijung Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

    IPC: H01L27/102 ,  H01L29/74

    Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

    Resistive memory device controlling bitline voltage
    35.
    发明授权
    Resistive memory device controlling bitline voltage 有权

    公开(公告)号：US11430515B2

    公开(公告)日：2022-08-30

    申请号：US17036004

    申请日：2020-09-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Cheonan Lee ,  Satoru Yamada ,  Junhee Lim

    IPC: G11C13/00 ,  H01L27/24

    Abstract: A resistive memory device includes a memory cell array, control logic, a voltage generator, and a read-out circuit. The memory cell array includes memory cells connected to bit lines. Each memory cell includes a variable resistance element to store data. The control logic receives a read command and generates a voltage control signal for generating a plurality of read voltages based on the read command. The voltage generator sequentially applies the read voltages to the bit lines based on the voltage control signal. The read-out circuit is connected to the bit lines. The control logic determines values of data stored in the memory cells by controlling the read-out circuit to sequentially compare values of currents sequentially output from the memory cells in response to the plurality of read voltages with a reference current.

    Semiconductor devices and methods of manufacturing the same
    36.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权

    公开(公告)号：US11329137B2

    公开(公告)日：2022-05-10

    申请号：US16927463

    申请日：2020-07-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Naoto Umezawa ,  Satoru Yamada ,  Junsoo Kim ,  Honglae Park ,  Chunhyung Chung

    IPC: H01L29/51 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49

    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.

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